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MAX1535A Datasheet, PDF (31/39 Pages) Maxim Integrated Products – Highly Integrated Level 2 SMBus Battery Charger
Highly Integrated Level 2 SMBus
Battery Charger
This describes a single-pole system. Since:
GMOUT
=
1
ACSI × RS2
the loop-transfer function simplifies to:
LTF = GMI
ROGMI
1+ SROGMI × CCI
The crossover frequency is given by:
fCO_ CI
=
GMI
2πCCI
For stability, choose a crossover frequency lower than
1/10th of the switching frequency:
CCI = GMI / (2π fCO-CI)
Choosing a crossover frequency of 30kHz and using the
component values listed in Figure 1 yields CCI > 5.4nF.
Values for CCI greater than 10 times the minimum value
may slow down the current-loop response excessively.
Figure 13 shows the Bode plot of the current-loop fre-
quency response using the values calculated above.
CCS Loop Compensation
The simplified schematic in Figure 14 is sufficient to
describe the operation of the MAX1535A when the input
current-limit loop (CCS) is in control. Since the output
capacitor’s impedance has little effect on the response
of the input current-limit loop, only a single pole is
required to compensate this loop. ACSS is the internal
gain of the current-sense amplifier. R1 is the input cur-
rent-sense resistor, R1 = 10mΩ in the typical application
circuits. ROGMS is the equivalent output impedance of
the GMS amplifier, which is greater than 10MΩ. GMS is
the charge-current amplifier transconductance =
1µA/mV. GMIN is the DC-to-DC converter’s input-referred
transconductance = (1/D) × GMOUT = (1/D) × 5A/V.
The loop-transfer function is given by:
LTF
=
GMIN
×
ACSS
×
RSI
×
GMS
1+
ROGMS
SROGMS ×
CCS
Since
GMIN
=
1,
ACSS × RS1
the
loop − transfer
function
simplifies to :
LTF = GMS
ROGMS
1+ SROGMS × CCS
The crossover frequency is given by:
fCO_ CS
=
GMS
2πCCS
For stability, choose a crossover frequency lower than
1/10th of the switching frequency:
CCS = 5×GMS / (2π fOSC)
Choosing a crossover frequency of 30kHz and using
the component values listed in Figure 1 yields CCS >
5.4nF. Values for CCS greater than 10 times the mini-
mum value may slow down the current-loop response
excessively. Figure 15 shows the Bode plot of the input
current-limit-loop frequency response using the values
calculated above.
MOSFET Drivers
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and high-
side switches. This is consistent with the variable duty
factor that occurs in the notebook computer environ-
ment where the battery voltage changes over a wide
range. An adaptive dead-time circuit monitors the DLO
output and prevents the high-side FET from turning on
until DLO is fully off. There must be a low-resistance,
low-inductance path from the DLO driver to the MOSFET
gate for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry in the MAX1535A inter-
prets the MOSFET gate as “off” while there is still charge
left on the gate. Use very short, wide traces measuring
10 squares to 20 squares or less (1.25mm to 2.5mm
wide if the MOSFET is 25mm from the device). Unlike
the DLO output, the DHI output uses a 50ns (typ) delay
time to prevent the low-side MOSFET from turning on
until DHI is fully off. The same layout considerations
should be used for routing the DHI signal to the high-
side MOSFET.
Since the transition time for a P-channel switch can be
much longer than an N-channel switch, the dead time
prior to the high-side P-channel MOSFET turning on is
more pronounced than in other synchronous step-down
regulators, which use high-side N-channel switches. On
the high-to-low transition, the voltage on the inductor’s
“switched” terminal flies below ground until the low-side
switch turns on. A similar dead-time spike occurs on
the opposite low-to-high transition. Depending upon the
magnitude of the load current, these spikes usually
have a minor impact on efficiency.
The high-side driver (DHI) swings from SRC to 5V
below SRC and has a typical impedance of 1Ω sourc-
ing and 4Ω sinking. The low-side driver (DLO) swings
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