MAX1535A Datasheet, PDF (12/39 Pages) Maxim Integrated Products – Highly Integrated Level 2 SMBus Battery Charger

Highly Integrated Level 2 SMBus
Battery Charger
Pin Description
PIN NAME
FUNCTION
1 DCIN DC Supply Voltage Input. Bypass DCIN to power ground (PGND) with a 1µF ceramic capacitor.
2
LDO
5.4V Linear-Regulator Output. The linear regulator powers the internal circuitry of the device. The input of the linear
regulator is supplied from DCIN. Bypass LDO with a 1µF ceramic capacitor to GND.
3
ACIN
AC Adapter Detect Input. This uncommitted comparator input can be used to detect if the AC adapter voltage is
available for charging.
4
REF 4.096V (Typical) Reference Voltage Output. Bypass REF with a 1µF ceramic capacitor to GND.
5 GND Analog Ground
6 CCS Input Current-Limit Regulation Loop Compensation Point. Connect a 0.01µF capacitor to GND.
7
CCI Charge-Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor to GND.
8
CCV ^{Charge-Voltage Regulation Loop Compensation Point. Connect a 20kΩ resistor in series with a 0.01µF capacitor}
to GND.
9 VMAX ^{Analog Control Input for Setting the Maximum Charge Voltage. The maximum charge voltage can never go above}
the limit set by VMAX. The ratio of maximum charge voltage to VMAX voltage is 5V/V.
10 IMAX ^{Analog Control Input for Setting the Maximum Charge Current. The maximum charge current can never go above}
the limit set by IMAX. The ratio of maximum charge current to IMAX voltage is 5A/V.
11 DAC DAC Voltage Output. Bypass DAC with a 0.1µF ceramic capacitor to GND.
12 V_DD Logic Circuitry Supply Voltage Input. The voltage range of V_DD is 2.7V to 5.5V.
13 THM Thermistor Voltage Input
14 SDA SMBus Data Input/Output. SDA is an open-drain output. An external pullup resistor is needed.
15 SCL SMBus Clock Input. An external pullup resistor is needed.
16
INT Interrupt Output. INT is an open-drain output. An external pullup resistor is needed.
17 I.C. Internally Connected Pin. Leave it unconnected or connect it to ground.
18 GND Analog Ground
19 BATT Battery Voltage Input
20 CSIN Negative Input to the Charge Current-Sense Amplifier
21 CSIP Positive Input to the Charge Current-Sense Amplifier. Connect a 10mΩ current-sense resistor from CSIP to CSIN.
22 PGND Power Ground
23 DLO Low-Side Power MOSFET Gate Driver Output. Connect DLO to the gate of the low-side N-channel MOSFET.
24 DLOV Low-Side Gate Driver Supply. Bypass DLOV with a 0.1µF ceramic capacitor to PGND.
25 DHIV High-Side Gate Driver Supply. Bypass DHIV with a 0.1µF ceramic capacitor to CSSN.
26 DHI High-Side Power MOSFET Gate Driver Output. Connect DHI to the gate of the high-side P-channel MOSFET.
27 SRC Source Connection for PDS and PDL Switch Drivers
28 CSSN Negative Input to the Input Current-Limit Sense Amplifier
29 CSSP ^{Positive Input to the Input Current-Limit Sense Amplifier. Connect a 10mΩ current-sense resistor from CSSP to}
CSSN.
30
PDL
System Load P-Channel MOSFET Switch Driver Output. When the MAX1535A is powered down, the PDL output is
pulled to ground through an internal 100kΩ resistor.
31
PDS
Power Source P-Channel MOSFET Switch Driver Output. When the MAX1535A is powered down, the PDS output
is pulled to SRC through an internal 1MΩ resistor.
32 ACOK ^{AC Detect Output. This high-voltage open-drain output is low impedance when ACIN is less than REF/2. The}
ACOK output remains low impedance when the MAX1535A is powered down.
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