71M6521DE Datasheet, PDF(33/107 Page) Teridian Semiconductor Corporation

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71M6521DE Datasheet, PDF (33/107 Pages) Teridian Semiconductor Corporation – Energy Meter IC

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71M6521DE/DH/FE Data Sheet

Interrupt Request register (IRCON)

MSB

LSB

EX6

IEX5

IEX4

IEX3

IEX2

Table 44: The IRCON Register

Bit

Symbol Function

IRCON.7

IRCON.6

IRCON.5

IRCON.4

IRCON.3

IRCON.2

IRCON.1

IRCON.0

IEX6

IEX5

IEX4

IEX3

IEX2

External interrupt 6 edge flag

External interrupt 5 edge flag

External interrupt 4 edge flag

External interrupt 3 edge flag

External interrupt 2 edge flag

Table 45: The IRCON Bit Functions

Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the

service routine is called (Signals T0ACK and T1ACK â port ISR â active high when the service routine is

called).

External Interrupts

The 71M6521DE/DH/FE MPU allows seven external interrupts. These are connected as shown in Table 46. The

direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling

sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive.

Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table

46.

External

Interrupt

Connection

Digital I/O High Priority

Digital I/O Low Priority

FWCOL0, FWCOL1

CE_BUSY

PLL_OK (rising), PLL_OK (falling)

EEPROM busy

XFER_BUSY OR RTC_1SEC

Polarity Flag Reset

see DIO_Rx

falling

rising

falling

automatic

manual

Table 46: External MPU Interrupts

FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description for more

detail.

SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each

interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. Note that

XFER_BUSY, RTC_1SEC, FWCOL0, FWCOL1, PLLRISE, PLLFALL, have their own enable and flag bits in addition

to the interrupt 6, 4, and 2 enable and flag bits.

IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags,

IE_XFER through IE_PB, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte,

common practice would be to clear them with a bit operation. This is to be avoided. The hardware implements bit

operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before the

write, its flag will be cleared unintentionally. The proper way to clear the flag bits is to write a byte mask consisting of

all ones except for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore

ones written to them.

Rev 2

Page: 33 of 107

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