MAX1067 Datasheet, PDF (28/30 Pages) Maxim Integrated Products – Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
⎡
⎢
THD = 20 × log^⎢
⎛
⎝
V₂₂
+ V₃₂
+ V₄₂
+
V₅₂
⎞
⎠
⎤
⎥
⎥
⎢
⎣⎢
V₁
⎥
⎦⎥
where V₁ is the fundamental amplitude and V₂ through
V₅ are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest fre-
quency component.
Supplies, Layout, Grounding, and
Bypassing
Use printed circuit (PC) boards with separate analog
and digital ground planes. Do not use wire-wrap
boards. Connect the two ground planes together at the
MAX1067/MAX1068 AGND terminal. Isolate the digital
supply from the analog with a low-value resistor (10Ω)
or ferrite bead when the analog and digital supplies
come from the same source (Figure 25).
Constraints on sequencing the power supplies and
inputs are as follows:
• Apply AGND before DGND.
• Apply AIN_ and REF after AV_DD and AGND are
present.
• DV_DD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
AIN_
AIN_
CS
CS
REF
SCLK
SCLK
1µF
DOUT
DOUT
+5V
AV_{DD MAX1067}
MAX1068
0.1µF 10Ω
DV_DD
0.1µF
AGND
AGND
DGND
GND
Figure 25. Powering AV_DD and DV_DD from a Single Supply
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV and a 1 LSB error with a +4.096V
full-scale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital lines (especially the SCLK and DOUT) parallel to one
another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the AV_DD power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
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