MAX1067 Datasheet, PDF (17/30 Pages) Maxim Integrated Products – Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
CS
1
SCLK
MSB
DIN
DOUT
8
LSB
0
MSB
16
24
LSB
S1 S0
DSPR*
DSEL*
ADC
STATE
t_ACQ
t_CONV
IDLE
*MAX1068 ONLY
Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
minimum high and low times are at least 93ns. External
clock-mode conversions with SCLK rates less than
125kHz can reduce accuracy due to leakage of the sam-
pling capacitor. DOUT changes from high-Z to logic low
after CS is brought low. Input data latches on the rising
edge of SCLK. The first SCLK rising edge begins loading
data into the command/configuration/control register from
DIN. The devices select the proper channel for conver-
sion on the rising edge of the 3rd SCLK cycle. Acquisition
begins immediately thereafter and ends on the falling
edge of the 6th clock cycle. The MAX1067/MAX1068
sample the input and begin conversion on the falling
edge of the 6th clock cycle. Setup and configuration of
the MAX1067/MAX1068 complete on the rising edge of
the 8th clock cycle. The conversion result is available
(MSB first) at DOUT on the falling edge of the 8th SCLK
cycle. To read the entire conversion result, 16 SCLK
cycles are needed. Extra clock pulses, occurring after the
conversion result has been clocked out and prior to the
rising edge of CS, cause zeros to be clocked out of
DOUT. The MAX1067/MAX1068 external clock 8-bit-wide
data-transfer mode requires 24 SCLK cycles for comple-
tion (Figure 10).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t_CSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1067/MAX1068 in shutdown.
External Clock 16-Bit-Wide Data-Transfer Mode
(MAX1068 Only)
Force DSPR high and DSEL high for SPI/QSPI/
MICROWIRE-interface mode. Logic high at DSEL allows
the MAX1068 to transfer data in 16-bit-wide words. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. The falling edge
of CS wakes the analog circuitry and allows SCLK to
clock in data. Ensure the duty cycle on SCLK is
between 45% and 55% when operating at 4.8MHz (the
maximum clock frequency). For lower clock frequen-
cies, ensure that the minimum high and low times are at
least 93ns. External-clock-mode conversions with SCLK
rates less than 125kHz can reduce accuracy due to
leakage of the sampling capacitor. DOUT changes from
high-Z to logic low after CS is brought low. Input data
latches on the rising edge of SCLK. The first SCLK rising
edge begins loading data into the command/configura-
tion/control register from DIN. The devices select the
proper channel for conversion and begin acquisition on
the rising edge of the 3rd SCLK cycle. Setup and con-
figuration of the MAX1068 completes on the rising edge
of the 8th clock cycle. Acquisition ends on the falling
edge of the 14th SCLK cycle. The MAX1068 samples
the input and begins conversion on the falling edge of
the 14th clock cycle. The conversion result is available
(MSB first) at DOUT on the falling edge of the 16th
SCLK cycle. To read the entire conversion result, 16
SCLK cycles are needed. Extra clock pulses, occurring
after the conversion result has been clocked out and
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