MAX1067 Datasheet, PDF (10/30 Pages) Maxim Integrated Products – Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Pin Description
PIN
MAX1067 MAX1068
1
3
NAME
FUNCTION
DOUT
Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE
mode and on SCLK’s rising edge in DSP mode (MAX1068 only). DOUT is high impedance
when CS is high.
2
4
SCLK
Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks
data out.
Serial Data Input. Use DIN to communicate with the command/configuration/control register.
3
5
DIN In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In DSP
mode, the falling edge of SCLK clocks in data at DIN.
4
6
EOC
End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a
conversion with the result available at DOUT. In external clock mode, EOC remains high.
5
7
AIN0 Analog Input 0
6
8
AIN1 Analog Input 1
7
9
AIN2 Analog Input 2
8
10
AIN3 Analog Input 3
9
15
REF ^{Reference Voltage Input/Output. VREF sets the analog voltage range. Bypass to AGND with}
a 10µF capacitor. Bypass with a 1µF (min) capacitor when using the internal reference.
10
16
REFCAP ^{Reference Bypass Capacitor Connection. Bypass to AGND with a 0.1µF capacitor when using}
internal reference. Internal reference and buffer shut down in external reference mode.
11
17
AGND Analog Ground. Connect to pin 18 (MAX1068) or pin 12 (MAX1067).
12
18
AGND Primary Analog Ground (Star Ground). Power return for AV_DD.
13
19
AV_DD Analog Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
Active-Low Chip-Select Input. Forcing CS high places the MAX1067/MAX1068 in shutdown
with a typical supply current of 0.6µA. In SPI/QSPI/MICROWIRE mode, a high-to-low
14
20
CS transition on CS activates normal operating mode. In DSP mode, after the initial CS transition
from high to low, CS can remain low for the entire conversion process (see the Operating
Modes section).
15
21
DGND Digital Ground
16
22
DV_DD Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.
—
1
DSPR ^{DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a}
conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.
Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-
—
2
DSEL transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not leave
DSEL unconnected.
—
11
AIN4 Analog Input 4
—
12
AIN5 Analog Input 5
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