MAX1067 Datasheet, PDF (25/30 Pages) Maxim Integrated Products – Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1067/MAX1068 support a
maximum f_SCLK of 4.8MHz. Figure 21a shows the
MAX1067/MAX1068 connected to a QSPI master and
Figure 21b shows the associated interface timing.
CS
SCK
MISO
QSPI
SS
CS
SCLK
DOUT
V_DD
MAX1067
MAX1068
Figure 21a. QSPI Connections
PIC16 with SSP Module and PIC17
Interface
The MAX1067/MAX1068 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
be synchronously transmitted and received simultane-
ously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 14-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the µC on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
SCLK
1
CS
DOUT*
*WHEN CS IS HIGH, DOUT = HIGH-Z
4
6
8
12
16
20
24
SAMPLING INSTANT
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
MSB
LSB
HIGH-Z
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
Table 7. Detailed SSPCON Register Contents
CONTROL BIT
WCOL
BIT7
SSPOV
BIT6
SSPEN
BIT5
CKP
SSPM3
SSPM2
SSPM1
SSPM0
X = Don’t care.
BIT4
BIT3
BIT2
BIT1
BIT0
SETTINGS
X
X
1
0
0
0
0
1
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
Write Collision Detection Bit
Receive Overflow Detection Bit
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial
port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
Synchronous Serial-Port Mode Select Bit. Sets SPI master-mode and
selects f_CLK = f_OSC / 16.
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