MAX1067 Datasheet, PDF (26/30 Pages) Maxim Integrated Products – Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Table 8. Detailed SSPSTAT Register Contents
CONTROL BIT
SMP
BIT7
CKE
D/A
P
S
R/W
UA
BF
X = Don’t care.
V_DD
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SETTINGS
0
1
X
X
X
X
X
X
V_DD
SCLK
DOUT
CS
MAX1067
MAX1068
SCK
SDI
I/O
PIC16/17
GND
Figure 22a. SPI Interface Connection for a PIC16/PIC17
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer-Full Status Bit
DSP Interface
The DSP mode of the MAX1068 only operates in exter-
nal clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1068. Use the same oscillator as
the DSP to provide the clock signal for the MAX1068.
The DSP provides the falling edge at CS to wake the
MAX1068. The MAX1068 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1068 in DSP mode. After the MAX1068
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1068 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1068 does not
operate in scan mode when using DSP mode.
SCLK
1
CS
1ST BYTE READ
4
6
8
DOUT*
0
0
0
0
0
0
0
0
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
2ND BYTE READ
12
16
D13 D12 D11 D10 D9 D8 D7 D6
MSB
24
D5 D4 D3 D2 D1 D0 S1 S0
LSB
HIGH-Z
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
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