MAX14820 Datasheet, PDF (26/29 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14820
IO-Link Device Transceiver
SPI Interface
The device communicates through an SPI-compatible
4-wire serial interface. The interface has three inputs—
clock (SCLK), chip select (CS), and data in (SDI)—and
one output, data out (SDO). The maximum SPI clock rate
for the device is 12MHz. The SPI interface complies with
clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 10 and Figure 11).
The SPI interface is not available when V₅ or V_L are not
present.
CS
SCLK
SDI
W
0
0
0
0
0
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED
Figure 10. SPI Write Cycle
CS
SCLK
SDI X
R
0
0
0
0
0
R1 R0
X
SDO
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED
= CLOCK EDGE AT WHICH LOGIC IS WRITTEN
Figure 11. SPI Read Cycle
D7 D6
D5 D4
D3 D2 D1
D0
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