MAX14820 Datasheet, PDF (17/29 Pages) Maxim Integrated Products – IO-Link Device Transceiver

MAX14820
IO-Link Device Transceiver
DO Fault Detection
The device registers a DoFault event when a short circuit
is present at the DO output for 440µs. A short condition
exists when the load current on the DO driver exceeds
the 200mA (typ) DO current limit. When a short-circuit
condition is detected, the DO driver enters autoretry
mode. In autoretry mode the device periodically checks
whether the error is still present. Autoretry attempts last
for 440µs (typ) and occur every 26ms (typ). When a
DoFault error is detected, the DoFault and DoFaultInt bits
are set, IRQ asserts, and the driver is turned off 440µs
(typ) after the start of the DO faults.
Reverse-Polarity Protection
The device is protected against reverse-polarity connec-
tions on V_CC, C/Q, DO, DI, and GND. Any combination
of these pins can be connected to DC voltages up to
40V (max). A short to 40V results in a current flow of less
than 500FA.
Ensure that the maximum voltage between any of these
pins does not exceed 40V.
5V and 3.3V Linear Regulators
The device includes two internal current-limited regulators
to generate 5V (V₅) and 3.3V (LDO33). V₅ is specified at
10mA when bypassed with a 0.1µF capacitor to ground.
Add the compensation network shown in Figure 7 to draw
up to 30mA from V₅. LDO33 is specified at 20mA. The
input of V₅, LDOIN, can be connected to V_P, the pro-
tected 24V supply output, or to another voltage in the 7V
to 36V range.
V₅ constitutes the supply for the logic block. The 5V LDO
can be disabled by connecting LDOIN to V₅. Apply an
external voltage from 4.75V to 5.25V to V₅ when the LDO
is disabled.
V5
MAX14820
LDO33
VL
0.1µF
5V
10Ω
1µF
3.3V
1µF
Figure 7. V₅ Compensation Network
Use the LDO33Dis bit in the Mode register to enable/
disable LDO33. See the Mode Register [R1, R0] = [1,1]
section for more information. V₅ and LDO33 are not pro-
tected against short circuits.
Power-Up
The C/Q and DO driver outputs and the UV output are
high impedance when V_CC, V₅, V_L, and/or LDO33 volt-
ages are below their respective undervoltage thresh-
olds during power-up. UV goes low and the drivers are
enabled when all these voltages exceed their respective
undervoltage lockout thresholds.
The drivers are automatically disabled if V_CC, V₅, or V_L
falls below its threshold.
Undervoltage Detection
The device monitors V_CC, V₅, V_L, and optionally LDO33
for undervoltage conditions. UV is high impedance when
any monitored voltage falls below its UVLO threshold.
V_CC, V₅, and V_L undervoltage detection cannot be dis-
abled. When V_CC falls below the V_CCUVLO threshold, the
UV24 and UV24Int bits are set, UV asserts high, and IRQ
asserts low.
The SPI register contents are unchanged while V₅ is pres-
ent, regardless of the state of V_CC and LDO33. The SPI
interface is not accessible and IRQ is not available when
UV is asserted due to a V₅ or V_L undervoltage event.
When the internal 3.3V LDO regulator voltage (V_LDO33)
falls below the LDO33 undervoltage lockout threshold,
the UV33Int bit in the Status register is set and IRQ
asserts. UV asserts if the UV33En bit in the Mode register
is set to 1.
The UV output deasserts once the undervoltage condi-
tion is removed; however, bits in the Status register and
the IRQ output are not cleared until the Status register
has been read.
Wake-Up Detection
The device detects an IO-Link wake-up condition on the
C/Q line in push-pull, high-side (PNP), or low-side (NPN)
operation modes. A wake-up condition is detected when
the C/Q output is shorted for 80Fs (typ). WU pulses low
for 190Fs (typ) when the device detects a wake-up pulse
on C/Q (Figure 5).
Set the WuIntEn bit in the Mode register to set the WuInt
bit in the Status register and generate an interrupt on
IRQ when a wake-up pulse is detected. WuInt is set
and IRQ asserts immediately after C/Q is released when
WuIntEn = 1.
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