MAX14827 Datasheet, PDF (25/41 Pages) Maxim Integrated Products – Integrated LED Driver

MAX14827
IO-Link Device Transceiver
Reverse-Polarity Protection
The MAX14827 is protected against reverse-polarity
connections on V24, C/Q, DO, DI, and GND. Any
combination of these pins can be connected to DC
voltages up to 65V (max), resulting in a current flow of
less than 1mA.
Ensure that the maximum voltage between any of these
pins does not exceed 65V.
Driver Short-Circuit Detection
The MAX14827 monitors the DO and C/Q driver outputs
for overcurrent and driver overheating conditions.
In pin-mode, the driver short-circuit current limit is set with
the CLK/TXEN/200mA input. IRQ/OC asserts when an
overcurrent or overheating condition occurs on either the
C/Q or DO driver. IRQ/OC deasserts when the overcurrent
or overheating condition is removed.
In SPI mode, the DO and C/Q are independently
monitored. Driver current limits for both drivers are set
using the CL1 and CL0 bits in the CURRLIM register.
When an overcurrent or overheating condition occurs on
C/Q, the CQFault and CQFaultInt bits are set and IRQ/OC
asserts. When an overcurrent or overheating condition
occurs on DO, the DOFault and DOFaultInt bits are set.
The CQFault and DOFault bits are cleared as soon as
the overcurrent or overheating conditions on the C/Q
and DO drivers are removed. IRQ/OC deasserts and the
CQFaultInt and DOFaultInt bits are cleared only when the
INTERRUPT register is read.
5V and 3.3V Linear Regulators
The MAX14827 includes two internal regulators to
generate 5V (V5) and 3.3V (V33).
The V5 regulator is capable of driving external loads
up to 30mA, including device and 3.3V LDO current
consumption. To drive larger loads, use an external
pass transistor to generate the required 5V. When using
an external transistor, connect REG to the base of the
transistor to regulate the voltage and connect V5 to the
emitter (Figure 10 ).
When the internal 5V linear regulator is not used, V5 is the
supply input for the internal analog and digital functions
and must be supplied externally. Ensure that V5 is present
for normal operation.
The 3.3V regulator is capable of driving external loads up
to 30mA. In SPI mode, the 3.3V LDO can be enabled/
disabled by setting the V33Dis bit in the Mode register.
V5 and V33 are not protected against short circuits.
Power-Up
The C/Q and DO driver outputs are high impedance
when V24, V5, VL, and/or V33 voltages are below their
respective undervoltage thresholds during power-up.
The drivers are automatically disabled if V24, V5, or VL
falls below its threshold.
Low Voltage and Undervoltage Detection
In SPI mode, the device monitors the V24 supply for
low voltage and undervoltage conditions. Low-voltage
warnings must be enabled in the MODE register.
When V₂₄ falls below the 16V (typ) low-voltage warning
threshold, the V24W bit in the STATUS register is set. If
V24WEn is set to 1, the V24WInt interrupt bit is also set
and IRQ/OC asserts.
When V24 falls below the 7.4V (typ) undervotlage lockout
(UVLO) threshold, the UV24 bit in the STATUS register is
set. Similarly, the UV24Int bit in the INTERRUPT register is
set and IRQ/OC asserts. UVLO monitoring and interrupts
cannot be disabled.
Wake-Up Detection
The MAX14827 detects an IO-Link wake-up condition
on the C/Q line in push-pull, high-side (PNP), or low-side
(NPN) operation modes. A wake-up condition is detected
when the C/Q output is shorted for 80µs (typ). WU pulses
low for 200µs (typ) when the device detects a wake-up
pulse on C/Q (Figure 5).
In SPI mode, the WuInt bit in the INTERRUPT registeris
set and IRQ/OC asserts when an IO-Link wake-up event
is detected.
Wake-up detection can be disabled in SPI mode by setting
the WU_Dis bit in the MODE register to 0. Wake-up
detection cannot be disabled in pin-mode.
The device includes a wake-up detection algorithm to
avoid false wake-up detection on C/Q. The false wake-up
blanking time is defined by the current limit blanking time.
In pin-mode, this is 128μs. In SPI-mode, this is set by the
CL_BL0 and CL_BL1 bits in the CURRLIM reigster.
Thermal Protection and Considerations
The internal LDOs and drivers can generate more power
than the package for the devices can safely dissipate.
Ensure that the driver and LDO loading is less than the
package can dissipate. Total power dissipation for the
device is calculated using the following equation:
P_TOTAL = P_C/Q + P_DO + P_V5 + P₃₃ + P₂₄ +
(2 x P_PU) + (2 x P_PD)
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