MAX14827 Datasheet, PDF (19/41 Pages) Maxim Integrated Products – Integrated LED Driver

MAX14827
IO-Link Device Transceiver
Pin Description (continued)
PIN
TQFN WLP
NAME
PIN
PARALLEL MODE
DESCRIPTION (SPI/PIN = high)
UARTSEL = Low
FUNCTION
MULTIPLEXED
MODE
(SPI/PIN = high)
UARTSEL = high
PIN MODE
(SPI/PIN = low)
8
A1
C/Q
C/Q Transceiver
Output/
Input
The C/Q driver can be controlled and
monitored with the logic input/output pins
or through the SPI interface. Drive TXEN
high to enable the C/Q driver. The logic on
the C/Q output is the inverse logic-level of
the signal in the TX input. RX is the logic
inverse of C/Q.
Drive TXEN high to enable
the C/Q driver. The logic on
the C/Q output is the inverse
logic-level of the signal in
the TX input. RX is the logic
inverse of C/Q.
Configure the C/Q driver
with the pin-mode inputs.
9
A2
V24
Power-Supply
Input
Bypass V24 to GND with a 1μF ceramic capacitor as close to the device as
possible.
10
A3
GND
Ground
11
A4
DO
DO Driver
Output
DO is the inverse logic level of the LO input.
The DO driver can be enabled/disabled,
configured, controlled, and monitored with
the logic input/output pins or through the SPI
interface.
DO is the inverse logic level
of the LO input. Configure
the DO driver with the pin-
mode inputs. DO cannot be
disabled in pin-mode.
12
A5
DI
DI Receiver
Input
The DI receiver can be monitored on the LI
output or through the SPI interface. The LI
output is the inverse logic-level of the signal
on the DI input.
The LI output is the inverse
logic-level of the signal on
the DI input. The DI receiver
cannot be disabled in pin-
mode.
13
B4
V33
3.3V Linear
Regulator
Output
Bypass V33 to GND with a 1μF capacitor as
close to the IC as possible. The V33 regulator
can be disabled through the SPI interface.
Bypass V33 to GND with a
1μF capacitor as close to the
IC as possible. V33 cannot
be disabled in pin-mode.
14
B5
VL
Logic-Level
Supply Input
VL defines the logic levels on all of the logic inputs and outputs. Apply a
voltage from 2.5V to 5.5V on VL. Bypass VL to GND with a 0.1μF ceramic
capacitor.
The LI output is the inverse logic-level of
The LI output is the inverse
15
C5
LI
DI Receiver
Logic Output
the signal on the DI input. Disable the LI
output through the SPI interface. LI is high
logic-level of the signal on
the DI input. LI cannot be
impedance when the DI_Dis bit is set.
disabled in pin-mode.
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