MAX15003 Datasheet, PDF (24/32 Pages) Maxim Integrated Products – Triple-Output Buck Controller with Tracking/Sequencing

Triple-Output Buck Controller with
Tracking/Sequencing
Type III: Compensation When f_CO < f_{ZERO, ESR}
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(f_{ZERO, ESR}) is usually much higher than unity
crossover frequency (f_CO). In this case, a Type III com-
pensation network is recommended (see Figure 7a).
V_OUT
C_CF
R_{I R1}
C_I
R2
R_F
C_F
-
g_M
V_REF +
COMP
Figure 7a. Type III Compensation Network
Use the following procedure to calculate the compen-
sation network components.
1) Select a crossover frequency, f_CO:
f_CO
≤
fSW
10
2) Calculate the LC double-pole frequency, f_LC :
f_LC
=
2π×
1
L × COUT
3) Select R_F ≥ 10kΩ.
4) Place a zero f_Z1 = ¹
at 0.75 x f_LC where
2π x R_F x C_F
C_F
=
1
2π×RF ×0.75×fLC
5) Calculate C_I for a target unity-gain crossover fre-
quency, f_C:
C_I
=
2π×fCO ×L×COUT ×VRAMP
VIN ×RF
Note: C_I is derived by setting the total loop gain at
GAIN
(dB)
crossover frequency to unity, e.g., G_EA(f_CO) x
G_MOD(f_CO) = 1V/V. The total loop gain can be
expressed logarithmically as follows:
3RD ASYMPTOTE
ωR_FC_I
1ST ASYMPTOTE
(ωR_IC_F)^-1
2ND ASYMPTOTE
(R_FR_I)^-1
4TH ASYMPTOTE
R_FR_I-1
5TH ASYMPTOTE
(ωR_IC_CF)^-1
1ST POLE
(AT ORIGIN)
1ST ZERO
(R_FC_F)^-1
2ND POLE
(R_IC_I)^-1
2ND ZERO
(R_IC_I)^-1
3RD POLE ^{ω(rad/sec)}
(R_FC_CF)^-1
Figure 7b. Type III Compensation Network Response
As shown in Figure 7b, a Type III compensation net-
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and higher frequency poles.
The locations of the zeros and poles should be such
that the phase margin peaks at f_CO.
Set the ratios of f_CO-to-f_Z and f_P-to-f_CO equal to one
another,
e.g.,
f_CO
f_Z
=f_C^fPO=
5
is
a
good
number
to
get
about
60° of phase margin at f_CO. Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
[ ] ^{20 × log}10 ^{2π × f}CO ^{× R}F ^{× C}I ⁺
( ) ^⎡
20
×
log₁₀
⎢
⎢
⎣
G_MOD(DC)
2π × f_CO ² × L × C_OUT
⎤
⎥
⎥
⎦
=
0dB
6) Place a second zero, f_Z2, at or below f_LC thereby
determining R₁.
R₁
=
1
2π×fZ2 ×CI
7) Place a pole (f_P1 = ¹
), at or below f_ZERO,ESR.
(2π x R1 x CI)
R₁
=
1
2π×fZERO,ESR ×CI
8) Place a second pole (f_P2 = ¹
) at or below
2π x R_F x C_CF
one-half the switching frequency.
C_CF
=
1
π×fSW ×RF
9) Calculate R2 using the following equation:
R₂
=
R₁ ×
VFB
VOUT −VFB
where V_FB = 0.6V.
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