MAX15003 Datasheet, PDF (12/32 Pages) Maxim Integrated Products – Triple-Output Buck Controller with Tracking/Sequencing

Triple-Output Buck Controller with
Tracking/Sequencing
Pin Description (continued)
PIN
NAME
FUNCTION
Controller 3 Enable/Tracking Input. See Figure 2.
When sequencing, EN/TRACK3 must be above 1.24V for the PWM controller 3 to start.
33 EN/TRACK3 Coincident tracking—connect the same resistive divider used for FB3, from Output 1 to EN/TRACK3 to
SGND.
Ratiometric tracking—connect EN/TRACK3 to analog ground.
34
COMP3 ^{Controller 3 Error Transconductance Amplifier Output. Connect COMP3 to the compensation feedback}
network.
Controller 3 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, R_ILIM3, from ILIM3 to SGND
35
ILIM3
to program the valley current-limit threshold from 50mV to 300mV. ILIM3 sources 20µA out to R_ILIM3. The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM3 to SGND to set the valley current limit. See Figure 11.
Controller 3 Positive Current-Sense Input. Connect CSP3 to the synchronous MOSFET source (connected to
36
CSP3
PGND3). When using a current-sense resistor, connect CSP3 to the PGND3 end of the current-sense
resistor.
Controller 3 Negative Current-Sense Input. Connect CSN3 to the synchronous MOSFET drain (connected to
37
CSN3
LX3). When using a current-sense resistor, connect CSN3 to the junction of low-side MOSFET’s source and
the current-sense resistor. See Figure 11.
38
BST3
Controller 3 High-Side Gate Driver Supply. Connect BST3 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
39
DH3
Controller 3 High-Side Gate Driver Output. DH3 drives the gate of the high-side MOSFET.
40
LX3
Controller 3 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX3.
41
DREG3
Controller 3 Low-Side Gate Driver Supply. Connect externally to REG and anode of the boost diode.
Connect a minimum of 0.1µF ceramic capacitor from DREG3 to PGND3.
42
DL3
Controller 3 Low-Side Gate Driver Output. DL3 is the gate driver output for the synchronous MOSFET.
Controller 3 Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
43
PGND3 the synchronous MOSFET, and the output filter capacitor’s return to PGND3. Connect externally to SGND at
a single point near the input capacitor return terminal.
Synchronization Input. Drive with a frequency at least 20% higher than three times the frequency
44
SYNC
programmed using the RT pin. The switching frequency is 1/3 the SYNC frequency. Connect SYNC to
SGND when not used.
45
SGND
Analog Ground Connection. Connect SGND and PGND_ together at one point near the input bypass
capacitor return terminal.
46
RT
Oscillator Timing Resistor Connection. Connect a 500kΩ to 45kΩ resistor from RT to SGND to program the
switching frequency from 200kHz to 2.2MHz.
47
PHASE
Phase Select Input. Connect PHASE to SGND for 120° out-of-phase operation between the controllers.
Connect to REG for in phase operation.
48
RESET
RESET Output. Open-drain RESET output releases after all PGOODs are released and timeout programmed
by CT finishes.
—
EP
Exposed Pad. Solder the exposed pad to a large SGND plane.
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