MAX15003 Datasheet, PDF (15/32 Pages) Maxim Integrated Products – Triple-Output Buck Controller with Tracking/Sequencing

Triple-Output Buck Controller with
Tracking/Sequencing
Internal Undervoltage Lockout (UVLO)
V_IN must exceed the default UVLO threshold before any
operation can commence. The UVLO circuitry keeps the
MOSFET drivers, oscillator, and all the internal circuitry
shut down to reduce current consumption. The UVLO
rising threshold is 4.05V with 350mV hysteresis.
Digital Soft-Start/Soft-Stop
The MAX15003 soft-start feature allows the load voltage
to ramp up in a controlled manner, eliminating output-
voltage overshoot. Soft-start begins after V_IN exceeds
the undervoltage lockout threshold and the enable
input is above 1.24V. The soft-start circuitry gradually
ramps up the reference voltage. This controls the rate
of rise of the output voltage and reduces input surge
currents during startup. The soft-start duration is 2048
clock cycles. The output voltage is incremented
through 64 equal steps. The output reaches regulation
when soft-start is completed, regardless of output
capacitance and load.
Soft-stop commences when the enable input falls
below 1.12V. The soft-stop circuitry ramps down the
reference voltage controlling the output voltage rate of
fall. The output voltage is decremented through 64
equal steps in 2048 clock cycles.
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO powered from IN
that provides power to the IC. Connect REG externally to
DREG to provide power for the low-side MOSFET gate
driver. Bypass REG to SGND with a minimum 2.2µF
ceramic capacitor. Place the capacitor physically close
to the MAX15003 to provide good bypassing. REG is
intended for powering only the internal circuitry and
should not be used to supply power to external loads.
REG can source up to 120mA. This current, I_REG,
includes quiescent current (I_Q) and gate drive current
(I_DREG):
I_REG = I_Q + [f_SW x Σ(Q_{GHS_} + Q_{GLS_})]
where Q_{GHS_} to Q_{GLS_} are the total gate charge of
each of the respective high- and low-side external
MOSFETs at V_GATE = 5V. f_SW is the switching frequen-
cy of the converter and I_Q is the quiescent current of
the device at the switching frequency.
MOSFET Gate Drivers
DREG_ is the supply input for the low-side MOSFET dri-
ver. Connect DREG_ to REG externally. Everytime the
low-side MOSFET switches on, high peak current is
drawn from DREG for a short amount of time. Adding
an RC filter (1Ω to 3.3Ω and 2.2F in parallel to 0.1µF
ceramic capacitors are typical) from REG to DREG_ fil-
ters out high-peak currents. Alternatively, DREG can be
connected to an external source (V_DREG-EXT). Note that
the DREG voltage should be high enough to fully
enhance the low-side MOSFET. To avoid partial
enhancing of the MOSFETs, use the V_DREG-EXT to set
the UVLO externally using EN1.
BST_ supplies the power for the high-side MOSFET dri-
vers. Connect the bootstrap diode from BST_ to DREG_
(anode at DREG_ and cathode at BST_). Connect a
bootstrap 0.1µF or higher ceramic capacitor between
BST_ and LX_. Though not always necessary, it may be
useful to insert a small resistor (4.7Ω to 22Ω) in series
with the BST_ pin and the cathode of the bootstrap
diode for additional noise immunity.
The high-side (DH_) and low-side (DL_) drivers drive
the gates of the external n-channel MOSFETs. The dri-
vers’ 2A peak source- and sink-current capability pro-
vides ample drive for the fast rise and fall times of the
switching MOSFETs. Faster rise and fall times result in
reduced switching losses.
The gate driver circuitry also provides a break-before-
make time (20ns typ) to prevent shoot-through currents
during transition.
Oscillator/Synchronization Input/Phase
Staggering (RT, SYNC, PHASE)
Use an external resistor at RT to program the
MAX15003 switching frequency from 200kHz to
2.2MHz. Choose the appropriate resistor at RT to cal-
culate the desired output switching frequency (f_SW):
f_SW (Hz) = 10¹¹/(R_RT + 1750) (Ω)
Connect an external clock at SYNC for external clock
synchronization. A rising clock edge on SYNC is inter-
preted as a synchronization input. If the SYNC signal is
lost, the internal oscillator takes control of the switching
rate, returning the switching frequency to that set by
R_RT. This maintains output regulation even with intermit-
tent SYNC signals. For proper synchronization, the
external frequency must be at least 20% higher than
three times the frequency programmed through the RT
input. The switching frequency is 1/3 the SYNC fre-
quency. Connect SYNC to SGND when not used.
Connect PHASE to SGND for 120° out-of-phase opera-
tion between the controllers. Connect PHASE to REG
for in-phase operation.
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