MAX15003 Datasheet, PDF (19/32 Pages) Maxim Integrated Products – Triple-Output Buck Controller with Tracking/Sequencing

Triple-Output Buck Controller with
Tracking/Sequencing
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents, and therefore, the
input capacitor must be carefully chosen to withstand
the input ripple current and keep the input voltage rip-
ple within design requirements. The 120° ripple phase
operation increases the frequency of the input capaci-
tor ripple current to thrice the individual converter
switching frequency. When using ripple phasing, the
worst-case input capacitor ripple current is when the
one converter with the highest output current is on.
The input voltage ripple comprises ∆V_Q (caused by the
capacitor discharge) and ∆V_ESR (caused by the ESR of
the input capacitor). The total voltage ripple is the sum of
∆V_Q and ∆V_ESR which peaks at the end of the on-cycle.
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
ESR =
∆V_ESR
⎛⎝⎜_ILOAD(MAX)
+
∆I_P−P
2
⎞⎠⎟
CIN
=
I_LOAD(MAX)
×
⎛
⎝⎜
V_OUT
V_IN
⎞
⎠⎟
∆V_Q × f_SW
where:
( ) _{∆IP−P}
=
V_IN − V_OUT × V_OUT
V_IN × f_SW × L
I_LOAD(MAX) is the maximum output current, ∆I_P-P is the
peak-to-peak inductor current, and f_SW is the switching
frequency.
For the condition with only one converter is on, calculate
the input ripple current using the following equation:
( ) _{ICIN(RMS) =ILOAD(MAX) ×}
V_OUT × V_IN − V_OUT
V_IN
The MAX15003 includes UVLO hysteresis to avoid pos-
sible unintentional chattering during turn-on. Use addi-
tional bulk capacitance if the input source impedance is
high. At lower input voltage, additional input capaci-
tance helps avoid possible undershoot below the under-
voltage lockout threshold during transient loading.
Output Capacitor Selection
The allowed output voltage ripple and the maximum devi-
ation of the output voltage during load steps determine
the required output capacitance and its ESR. The output
ripple is mainly composed of ∆V_Q (caused by the capaci-
tor discharge) and ∆V_ESR (caused by the voltage drop
across the equivalent series resistance of the output
capacitor). The equations for calculating the output
capacitance and its ESR are:
C_OUT
=
∆I_P−P
8 × ∆V_Q × f_SW
ESR = ^{2 × ∆VESR}
∆I_P−P
∆V_ESR and ∆V_Q are not directly additive because they
are out of phase from each other. If using ceramic
capacitors, which generally have low ESR, ∆V_Q domi-
nates. If using electrolytic capacitors, ∆V_ESR domi-
nates.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with a greater
duty cycle. The response time (t_RESPONSE) depends on
the gain bandwidth of the converter (see the
Compensation Design Guidelines section). The resis-
tive drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL, and the capacitor dis-
charge cause a voltage droop during the load-step
(I_STEP). Use a combination of low-ESR tantalum/alu-
minum electrolytic and ceramic capacitors for better
load-transient and voltage-ripple performance. Surface-
mount capacitors and capacitors in parallel help
reduce the ESL. Keep the maximum output voltage
deviation below the tolerable limits of the electronics
being powered.
Use the following equations to calculate the required
ESR, ESL, and capacitance value during a load step:
ESR = ^∆VESR
I_STEP
C_OUT
= ^{ISTEP × tRESPONSE}
∆V_Q
ESL = ^{∆VESL × tSTEP}
I_STEP
where I_STEP is the load step, t_STEP is the rise time of the
load step, and t_RESPONSE is the response time of the
controller.
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