MAX1513 Datasheet, PDF (22/28 Pages) Maxim Integrated Products – TFT-LCD Power-Supply Controllers

TFT-LCD Power-Supply Controllers
The DC loop gain (A_DC) is approximately:
A_DC
=
R2
R1 + R2
×
1- D
0.554 × R_CS
×
V_MAIN
I_MAIN(EFF)
where R1 and R2 are the feedback-divider resistors
(Figure 1), D is the duty cycle, I_MAIN(EFF) is the effec-
tive maximum output current as described in the
Inductor Selection section, 0.554 is the gain of the cur-
rent-sense amplifier, and R_CS is the equivalent sense-
resistor value given by:
R_CS = SF × R_L(TYP)
where R_L(TYP) is the typical value of the inductor DCR,
and SF is either 1 or the scale factor in step 5 of the
Current-Sense Network Selection section.
The frequency of the dominant pole is:
f_P(DOMINANT)
=
I_MAIN(EFF)
2π × V_MAIN × C_OUT
The frequency of the RHP zero is:
( ) ^f_Z(RHP)
=
1- D² ×
V_MAIN
2π × L × I_MAIN(EFF)
The frequency of the ESR zero is:
f_Z(ESR)
=
2π ×
1
R_ESR ×
C_OUT
The unity-gain crossover frequency is:
f_CROSSOVER = A_DC × f_P(DOMINANT)
For stable operation, select an output capacitor with
enough capacitance and a low enough ESR to ensure
that the dominant pole is low enough so the loop gain
reaches unity well before either the ESR zero or the
RHP zero, the lower of which should preferably occur at
or above 5 times the unity-gain frequency as long as
the two zeros are well separated. Calculate the mini-
mum output capacitance for stable operation using:
[ ] ^COUT(MIN)
=
2π ×
5 × A_DC × I_MAIN(EFF)
min f_Z(RHP), f_Z(ESR) × V_MAIN
If the RHP zero and the ESR zero occur simultaneously,
place the dominant pole so that the unity-gain frequen-
cy is less than 1/10th the frequency of the zeros.
Calculate the minimum output capacitance for stable
operation using:
C_OUT(MIN)
=
10 × A_DC × I_MAIN(EFF)
2π × f_Z × V_MAIN
where f_Z is the frequency of the RHP zero and the
ESR zero.
Using the typical operating circuit in Figure 1 as an
example: the duty cycle is 0.67, the effective maximum
output current is 500mA, the inductor is 2.2µH with a
typical DCR of 24mΩ, and the output capacitor is 10µF
with a maximum ESR of 20mΩ. The scale factor for the
current-sense network is 1, so R_CS is 24mΩ. The DC
loop gain A_DC is 62, the RHP zero is at 236kHz, and the
ESR zero is at 796kHz. Since the frequency of the ESR
zero is higher than that of the RHP zero, the unity-gain
crossover frequency should be determined based on
the RHP zero. The minimum output capacitance for sta-
ble operation is:
C_OUT(MIN)
=
5 × 62 × 500mA
2π × 236kHz × 15V
≈
6.97µF
Lead or lag compensation can be useful to compen-
sate for particular component choices or to optimize
the transient response for various output capacitor or
inductor values.
Adding lead compensation (the R3/C1 network from
V_MAIN to FB in Figure 11) increases the loop band-
width, which can increase the speed of response to
transients. Too much speed can destabilize the loop
and is not needed or recommended for Figure 1’s com-
ponents. Lead compensation adds a zero-pole pair,
providing gain at higher frequencies and increasing
loop bandwidth. The frequencies of the zero and pole
for lead compensation depend on the feedback-divider
resistors and the RC network between V_MAIN and FB.
The frequencies of the zero and pole for the lead com-
pensation are:
f_{Z _LEAD}
=
1
2π × ₍R1 + R3₎ ×
C1
f_{P _LEAD}
=
2π ×
⎛⎝⎜_{R3 +}
1
R1 ×
R1 +
R2 ⎞
R2 ⎠⎟
×
C1
At high frequencies, R3 is effectively in parallel with R1,
determining the amount of added high-frequency gain.
If R3 is very large, there is no added gain and as R3
approaches zero, the added gain approaches the
inverse of the feedback-divider’s attenuation. A typical
value for R3 is greater than 1/2 of R1. The value of C1
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