MAX1471_11 Datasheet, PDF (22/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 7. Configuration Register (Address: 0x1)
BIT ID
X
BIT NAME
Don’t care
BIT LOCATION
(0 = LSB)
7
POWER-UP
STATE
0
GAINSET
Gain set
6
1
FSKCALLSB
FSK accurate
calibration
5
0
DOUT_FSK FSKOUT enable
4
0
DOUT_ASK ASKOUT enable
3
0
TOFF_PS1 Off-timer prescale
2
0
TOFF_PS0 Off-timer prescale
1
0
DRX_MODE
Receive mode
0
0
FUNCTION
Don’t care.
0 = LNA low-gain state.
1 = LNA high-gain state.
For manual gain control, enable the AGC (AGC_EN =
1), set LNA gain state to desired setting, then disable
the AGC (AGC_EN = 0).
FSKCALLSB = 1 enables a longer, more accurate
FSK calibration.
FSKCALLSB = 0 provides for a quick, less accurate
FSK calibration.
This bit enables the FDATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)
This bit enables the ADATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)
Sets LSB size for the off timer. (See the Off Timer
section.)
1 = Discontinuous receive mode. (See the
Discontinuous Receive Mode section.)
0 = Continuous receive mode. (See the Continuous
Receive Mode section.)
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace con-
necting a 100nH inductor adds an extra 10nH of induc-
tance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power lane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all V_DD or HVIN connections.
22 ______________________________________________________________________________________