MAX1471_11 Datasheet, PDF (18/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
CS
SCLK
DIO
0
0
1
0
A3 A2 A1 A0 0
0
0
0
0
0
0
0
READ
COMMAND
ADDRESS
DATA
CS
R7 R6
R5 R4 R3 R2
REGISTER DATA
R1 R0
R7
R0
REGISTER
DATA
16 BITS OF DATA
SCLK
DIO
0
0
1
0 A3 A2 A1 A0 0
0
0
0
0
0
0
0
READ
COMMAND
ADDRESS
DATA
Figure 11. Read Command in 3-Wire Interface
R7 R6 R5 R4 R3 R2 R1 A3
REGISTER DATA
8 BITS OF DATA
Table 3. Command Bits
C[3:0]
0x0
0x1
0x2
0x3
0x4–0xF
DESCRIPTION
No operation
Write data
Read data
Master reset
Not used
AGC Dwell Timer Register (Address: 0xA)
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
The AGC dwell time is dependent on the crystal fre-
quency and the bit settings of the AGC dwell timer reg-
ister. To calculate the dwell time, use the following
equation:
Dwell Time = ^2Reg0xA
f_XTAL
where Reg 0xA is the value of register 0xA in decimal.
To calculate the value to write to register 0xA, use the
following equation and use the next integer higher than
the calculated result:
Reg 0xA ≥ 3.3 x log₁₀ (Dwell Time x f_XTAL)
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to-
zero (NRZ) data, set the dwell to greater than the peri-
od of the longest string of zeros or ones. For example,
using Manchester code at 315MHz (f_XTAL =
9.509375MHz) with a data rate of 4kbps (bit period =
125µs), the dwell time needs to be greater than 250µs:
Reg 0xA ≥ 3.3 x log₁₀ (250µs x 9.509375MHz) ≈11.14
Choose the register value to be the next integer value
higher than 11.14, which is 12 or 0x0C hex.
The default value of the AGC dwell timer on power-up
or reset is 0x0D.
Calibration
The MAX1471 must be calibrated to ensure accurate
timing of the off timer in discontinuous receive mode or
when receiving FSK signals. The first step in calibration
is ensuring that the oscillator frequency register
(address: 0x3) has been programmed with the correct
divisor value (see the Oscillator Frequency Register
section). Next, enable the mixer to turn the crystal dri-
ver on.
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