MAX1471_11 Datasheet, PDF (19/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 4. Register Summary
REGISTER
A[3:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
REGISTER NAME
DESCRIPTION
Power configuration
Configuration
Control
Oscillator frequency
Off timer—t_OFF
(upper byte)
Off timer—t_OFF
(lower byte)
CPU recovery timer—t_CPU
RF settle timer—t_RF
(upper byte)
RF settle timer—t_RF
(lower byte)
Status register (read only)
AGC dwell timer
Enables/disables the LNA, AGC, mixer, baseband, peak detectors, and sleep mode
(see Table 6).
Sets options for the device such as output enables, off-timer prescale, and
discontinuous receive mode (see Table 7).
Controls AGC lock, peak-detector tracking, as well as polling timer and FSK
calibration (see Table 8).
Sets the internal clock frequency divisor. This register must be set to the integer
result of f_XTAL/100kHz (see the Oscillator Frequency Register section).
Sets the duration that the MAX1471 remains in low-power mode when DRX is active
(see Table 10).
Increases maximum time the MAX1471 stays in lower power mode while CPU wakes
up when DRX is active (see Table 11).
During the time set by the settle timer, the MAX1471 is powered on with the peak
detectors and the data outputs disabled to allow time for the RF section to settle.
DIO must be driven low at any time during t_LOW = t_CPU + t_RF or the timer sequence
restarts (see Table 12).
Provides status for PLL lock, AGC state, crystal operation, polling timer, and FSK
calibration (see Table 9).
Controls the dwell (release) time of the AGC.
Calibrate the polling timer by setting POL_CAL_EN = 1
in the configuration register (register 0x1). Upon com-
pletion, the POL_CAL_DONE bit in the status register
(register 0x8) is 1, and the POL_CAL_EN bit is reset to
zero. If using the MAX1471 in continuous receive
mode, polling timer calibration is not needed.
FSK receiver calibration is a two-step process. Set
FSKCALLSB = 1 (register 0x1) or to reduce the calibra-
tion time, accuracy can be sacrificed by setting the
FSKCALLSB = 0. Next, initiate FSK receiver calibration,
set FSK_CAL_EN = 1. Upon completion, the
FSK_CAL_DONE bit in the status register (register 0x8)
is one, and the FSK_CAL_EN bit is reset to zero.
When in continuous receive mode and receiving FSK
data, recalibrate the FSK receiver after a significant
change in temperature or supply voltage. When in dis-
continuous receive mode, the polling timer and FSK
receiver (if enabled) are automatically calibrated during
every wake-up cycle.
Off Timer (t_OFF)
The first timer, t_OFF (see Figure 12), is a 16-bit timer
that is configured using: register 0x4 for the upper byte,
register 0x5 for the lower byte, and bits PRESCALE1
and PRESCALE0 in the configuration register (register
0x1). Table 10 summarizes the configuration of the t_OFF
timer. The PRESCALE1 and PRESCALE2 bits set the
size of the shortest time possible (t_OFF time base). The
data written to the t_OFF registers (0x4 and 0x5) is multi-
plied by the time base to give the total t_OFF time. On
power-up, the off timer registers are set to zero and
must be written before using DRX mode.
During t_OFF, the MAX1471 is operating with very low
supply current (5.0µA typ), where all of its modules are
turned off, except for the t_OFF timer itself. Upon com-
pletion of the t_OFF time, the MAX1471 signals the user
by asserting DIO low.
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