MAX1146 Datasheet, PDF (21/25 Pages) Maxim Integrated Products – Multichannel, True-Differential, Serial, 14-Bit ADCs

Multichannel, True-Differential,
Serial, 14-Bit ADCs
CS
SCK
MISO
VDD
QSPI
SS
Figure 17. QSPI Connections
CS
SCLK
DOUT
MAX1146–
MAX1149
VDD
V_DD
SCLK
DOUT
CS
MAX1146–
MAX1149
SCK
SDI
I/O
PIC16/PIC17
GND
GND
Figure 18. SPI Interface Connection for a PIC16/PIC17
Controller
Table 8. Detailed SSPCON Register Content
CONTROL BIT
PICI6/PICI7
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
SSPOV
Bit 7
Bit 6
X
Write collision detection bit.
X
Receive overflow detect bit.
SSPEN
Bit 5
Synchronous serial port enable bit:
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial-port pins.
CKP
SSPM3
SSPM2
SSPM1
SSPM0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Clock polarity select bit. CKP = 0 for SPI master mode selection.
0
0
Synchronous serial port mode select bit. Sets SPI master mode and selects
0
FCLK = fOSC / 16.
1
Table 9. Detailed SSPSTAT Register Content
CONTROL BIT
MAX1146–MAX1149
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP
Bit 7
0
SPI data input sample phase. Input data is sampled at the middle of the data
output time.
CKE
Bit 6
1
SPI clock edge select bit. Data is transmitted on the rising edge of the serial
clock.
D/A
Bit 5
P
Bit 4
S
Bit 3
R/W
Bit 2
UA
Bit 1
BF
Bit 0
X
Data address bit.
X
Stop bit.
X
Start bit.
X
Read/write bit information.
X
Update address.
X
Buffer full status bit.
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