MAX1146 Datasheet, PDF (11/25 Pages) Maxim Integrated Products – Multichannel, True-Differential, Serial, 14-Bit ADCs

Multichannel, True-Differential,
Serial, 14-Bit ADCs
Pin Description
PIN
MAX1148 MAX1146
MAX1149 MAX1147
NAME
FUNCTION
1
1
CH0
2
2
CH1
3
3
CH2
4
4
CH3
Analog Inputs
5
—
CH4
6
—
CH5
7
—
CH6
8
—
CH7
9
9
COM
Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in
unipolar and bipolar mode.
10
10
SHDN ^{Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current}
to 0.2µA. Driving shutdown high enables the devices.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital
11
11
REF conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the
MAX1147/MAX1149 VREF is +2.500V.
Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01µF
12
12
REFADJ capacitor. Connect REFADJ to V_DD to disable the internal bandgap reference and reference-
buffer amplifier.
13
13
AGND Analog Ground
14
14
DGND Digital Ground
15
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is
high impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion
16
16
SSTRB
begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high
(external clock mode).
17
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high
impedance when CS is high.
18
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19
19
SCLK ^{Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed}
in external clock mode. (Duty cycle must be 40% to 60%.)
20
20
VDD Positive Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
—
5–8
N.C. No Connection. Not internally connected.
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