MAX1146 Datasheet, PDF (12/25 Pages) Maxim Integrated Products – Multichannel, True-Differential, Serial, 14-Bit ADCs

Multichannel, True-Differential,
Serial, 14-Bit ADCs
Detailed Description
The MAX1146–MAX1149 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 14-bit digital
output. A flexible serial interface provides easy inter-
face to microprocessors (µPs). Figure 4 shows the typi-
cal application circuit and Figure 5 shows a functional
diagram of the MAX1148/MAX1149.
True-Differential Analog Input and
Track/Hold
The MAX1146–MAX1149 analog input architecture con-
tains an analog input multiplexer (MUX), two T/H
capacitors, T/H switches, a comparator, and two
switched capacitor digital-to-analog converters (DACs)
(Figure 6).
ANALOG
INPUTS
2.2µF
CH0
VDD
CH1
CH2 _MAX1148
CH3 _MAX1149 SHDN
CH4
SCLK
CH5
CS
CH6
DIN
CH7
SSTRB
REF
DOUT
COM
REFADJ
AGND DGND
0.1µF
10Ω
4.7µF
VDD
VDD
0.01µF
I/O
SCK
I/O µP
MOSI
I/O
MISO
VSS
Figure 4. Typical Application Circuit
CS
SCLK
DIN
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REFADJ
REF
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INTERNAL
CLOCK
ANALOG
INPUT
MUX
OUTPUT
SHIFT
REGISTER
T/H
CLOCK
IN
SAR
ADC
OUT
REF
+1.250V
BANDGAP
REFERENCE
20kΩ
AV = 2.0V/V
MAX1149
Figure 5. Functional Diagram
DOUT
SSTRB
VDD
DGND
AGND
In single-ended mode, the analog input MUX connects
IN+ to the selected input channel and IN- to COM. In
differential mode, IN+ and IN- are connected to the
selected analog input pairs such as CH0/CH1. Select
the analog input channels according to Tables 1–5.
The analog input multiplexer switches to the selected
channel on the control byte’s fifth SCLK falling edge. At
this time, the T/H switches are in the track position and
CT/H+ and CT/H- track the analog input signal. At the
control byte’s eighth SCLK falling edge, the MUX opens
and the T/H switches move to the hold position, retain-
ing the charge on CT/H+ and CT/H- as a sample of the
input signal. See Figures 8–11 for input MUX and T/H
switch positioning.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator-input voltage to
0 within the limits of 14-bit resolution. This action
requires 15 conversion clock cycles and is equivalent
to transferring a charge of 18pF × (VIN+ - VIN-) from
CT/H+ and CT/H- to the binary-weighted capacitive
DAC, forming a digital representation of the analog
input signal.
After conversion, the T/H switches move from the hold
position to the track position and the MUX switches
back to the last specified position. In internal clock
mode, the conversion is complete on the rising edge of
SSTRB. In external clock mode, the conversion is com-
plete on the eighteenth SCLK falling edge.
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, the acquisi-
tion time lengthens. The MAX1146–MAX1149 provide
three SCLK cycles (tACQ) in which the T/H capacitance
must acquire a charge representing the input signal,
typically the last three SCLKs of the control word. The
input source impedance (RSOURCE) should be mini-
mized to allow the T/H capacitance to charge within
this allotted time.
tACQ = 11.5 × (RSOURCE + RIN) × CIN
where RSOURCE is the analog input source impedance,
RIN is 2.6kΩ (which is the sum of the analog input MUX
and T/H switch resistances), and CIN is 18pF (which is
the sum of CT/H+, CT/H-, and input stray capacitance).
To minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to AGND. This input capacitor reduces the input’s
AC impedance but forms an RC filter with the source
impedance, limiting the analog input bandwidth. For
larger source impedance, use a buffer amplifier such as
the MAX4430 to maintain analog input signal integrity.
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