MAX1146 Datasheet, PDF (19/25 Pages) Maxim Integrated Products – Multichannel, True-Differential, Serial, 14-Bit ADCs

Multichannel, True-Differential,
Serial, 14-Bit ADCs
+5V
IN
SAR
ADC
REF
MAX1146–
MAX1149
REFERENCE
BUFFER
DISABLED
20kΩ
1.250V
BANDGAP
REFERENCE
REF
3.000V _OUT MAX6163
0.1µF
REFADJ
GND
+5V
VDD
DGND
0.1µF
AGND
Figure 12. External Reference Applied to REF
Method 1 allows the direct application of an external
reference from 1.5V to VDD + 50mV. The REF input
impedance is typically 10kΩ. During conversion, an
external reference at REF must deliver up to 210µA and
have an output impedance less than 10Ω. Bypass REF
with a 0.1µF capacitor to AGND to improve its output
impedance.
Method 2 utilizes the internal reference buffer to reduce
the external reference load. The REFADJ input imped-
ance is typically 20kΩ. During a conversion, an external
reference at REFADJ must deliver at least 100µA and
have an output impedance less than 100Ω. The
MAX1146/MAX1148 reference buffer has a 3.277V/V
gain and the MAX1147/MAX1149 has a gain of
2.000V/V. The external reference voltage at REFADJ
multiplied by the reference buffer gain is the SAR ADC
reference voltage. This reference appears at REF and
must be from 1.5V to VDD + 50mV. Bypass REFADJ
Table 7. Full Scale and Zero Scale
+3.3V
24kΩ
100kΩ
510kΩ
0.047µF
MAX1146–
MAX1149
REFADJ
Figure 13. Reference Adjust Circuit
with a 0.01µF capacitor and bypass REF with a 2.2µF
capacitor to AGND.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Output data coding for the MAX1146–MAX1149 is bina-
ry in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = (VREF/2^N), where N is the
number of bits (14). Code transitions occur halfway
between successive-integer LSB values. Figure 14 and
Figure 15 show the input/output (I/O) transfer functions
for unipolar and bipolar operations, respectively.
Serial Interfaces
The MAX1146–MAX1149 feature a serial interface that
is fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the
serial clock for the ADCs. Select a clock frequency up
to 2.1MHz.
SPI and MICROWIRE Interface
When using an SPI (Figure 16a) or MICROWIRE interface
(Figure 16b), set CPOL = CPHA = 0. Two 8-bit readings
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
INPUT AND OUTPUT
MODES
UNIPOLAR MODE
ZERO SCALE
FULL SCALE
NEGATIVE FULL
SCALE
BIPOLAR MODE
ZERO SCALE
POSITIVE FULL
SCALE
Single-Ended Mode
VCOM
VREF + VCOM
−_VREF
2
+ V_COM
VCOM
+V_{REF + VCOM}
2
Differential Mode
VIN-
VREF + VIN-
−_VREF
2
+ V_IN−
Note: The common mode range for the analog inputs is from AGND to VDD.
VIN-
+V_REF
2
+ V_IN−
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