MAX1080 Datasheet, PDF (20/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE
Full Scale
Zero Scale
VREF + VCOM
VCOM
Positive
Full Scale
VREF / 2
+ V_COM
BIPOLAR MODE
Zero
Scale
VCOM
Negative
Full Scale
-VREF / 2
+ V_COM
SUPPLIES
V_DD1
GND
V_DD2
*R = 10Ω
V_DD1
*OPTIONAL
GND
COM VDD2
MAX1080
MAX1081
V_DD DGND
DIGITAL
CIRCUITRY
Figure 16. Power-Supply Grounding Connection
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10Ω resis-
tor can be connected as a lowpass filter (Figure 16).
High-Speed Digital Interfacing with QSPI
The MAX1080/MAX1081 can interface with QSPI using
the circuit in Figure 17 (f_SCLK = 4.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the eight channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
TMS320LC3x Interface
Figure 18 shows an application circuit to interface the
MAX1080/MAX1081 to the TMS320 in external clock
mode. Figure 19 shows the timing diagram for this inter-
face circuit.
Use the following steps to initiate a conversion in the
MAX1080/MAX1081 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input
clock. CLKX and CLKR on the TMS320 are connect-
ed to the MAX1080/MAX1081’s SCLK input.
2) The MAX1080/MAX1081’s CS pin is driven low by
the TMS320’s XF_ I/O port to enable data to be
clocked into the MAX1080/MAX1081s’ DIN pin.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1080/MAX1081 to initiate a conversion and
place the device into normal operating mode. See
Table 3 to select the proper XXXXX bit values for your
specific application.
4) The MAX1080/MAX1081s’ SSTRB output is moni-
tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the con-
version is in progress and data is ready to be
received from the device.
5) The TMS320 reads in 1 data bit on each of the next
16 rising edges of SCLK. These data bits represent
the 10 + 2-bit conversion result followed by 4 trailing
bits, which should be ignored.
6) Pull CS high to disable the MAX1080/MAX1081 until
the next conversion is initiated.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
from a straight line on an actual transfer function. This
straight line can be a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1080/MAX1081
are measured using the best-straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
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