MAX1080 Datasheet, PDF (18/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
fast power-down (FASTPD) or reduced-power (REDP)
mode instead of in full power-up can further reduce
power consumption. This is achieved by using the
sequence shown in Figure 12a.
Figure 10b shows the MAX1081’s power consumption
for one- or eight-channel conversions utilizing FULLPD
mode (PD1 = PD0 = 0), an external reference, and the
maximum clock speed. One dummy conversion to
power up the device is needed, but no wait time is nec-
essary to start the second conversion, thereby achiev-
ing lower power consumption at up to half the full
sampling rate.
Using Fast Power-Down and Reduced Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sam-
pling rate. Figure 11 shows the MAX1081’s power con-
sumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP
mode (PD1 = 1, PD0 = 0), and for comparison, normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
power consumption using the specified power-down
mode, with the internal reference and conversion con-
trolled at the maximum clock speed. The clock speed
in FASTPD or REDP should be limited to 4.8MHz for the
MAX1080/MAX1081. FULLPD mode may provide
increased power savings in applications where the
MAX1080/MAX1081 are inactive for long periods of
time, but intermittent bursts of high-speed conversions
are required. Figure 12b shows FASTPD and REDP tim-
ing.
Internal and External References
The MAX1080/MAX1081 can be used with an internal
or external reference. An external reference can be
connected directly at REF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at
REF for the MAX1080/MAX1081. The internally trimmed
1.22V reference is buffered with a 2.05V/V gain.
Internal Reference
The MAX1080/MAX1081s’ full-scale range with the inter-
nal reference is 2.5V with unipolar inputs and ±1.25V
with bipolar inputs. The internal reference voltage is
adjustable by ±100mV with the circuit in Figure 13.
WAIT 1.4ms (7 x RC)
DIN
REFADJ
1
00
FULLPD
1.22V
2.5V
REF
I_VDD1 + I_VDD2
2.5mA
1
10
1
00
1
REDP
DUMMY CONVERSION
FULLPD
1.22V
0V
γ = RC = 17kΩ x 0.01µF
2.5V
0V
2.5mA
1.3mA OR 0.9mA
0V
2.5mA
0mA
Figure 12a. Full Power-Down Timing
DIN
REF
I_VDD1 + I_VDD2
1
10
REDP
2.5V (ALWAYS ON)
2.5mA
0.9mA
1
10
REDP
2.5mA
0.9mA
1
01
FASTPD
2.5mA
1.3mA
Figure 12b. FASTPD and REDP Timing
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