MAX1080 Datasheet, PDF (14/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Table 3. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
START
SEL2
SEL1
BIT 4
SEL0
BIT 3
UNI/BIP
BIT 2
SGL/DIF
BIT 1
PD1
BIT 0
(LSB)
PD0
BIT
7(MSB)
6
5
4
3
NAME
START
SEL2
SEL1
SEL0
UNI/BIP
2
SGL/DIF
1
PD1
0(LSB)
PD0
DESCRIPTION
The first logic “1” bit after CS goes low defines the beginning of the control byte.
These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to V_REF can be converted; in bipolar mode, the differential signal can
range from -V_REF/2 to +V_REF/2.
1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conver-
sions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential
mode, the voltage difference between two channels is measured (Tables 1 and 2).
Select operating mode.
PD1
PD0
Mode
0
0
Full power-down
0
1
Fast power-down
1
0
Reduced power
1
1
Normal operation
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros, two sub-LSB bits, and one
trailing zero. The total conversion time is a function of
the serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar input mode, the output is two’s
complement (Figure 15). Data is clocked out on the ris-
ing edge of SCLK in MSB-first format.
Serial Clock
The external clock not only shifts data in and out but
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 SCLK rising edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 7 shows the detailed serial-interface
timings.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V_DD1 and V_DD2
are applied.
OR
The first high bit clocked into DIN after bit 4 of a con-
version in progress is clocked onto the DOUT pin.
Once a start bit has been recognized, the current conver-
sion may only be terminated by pulling SHDN low.
The fastest the MAX1080/MAX1081 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 8 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
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