MAX1080 Datasheet, PDF (11/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Detailed Description
The MAX1080/MAX1081 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 10-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1080/MAX1081.
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1080/
MAX1081s’ input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 1 and 2.
The MAX1080/MAX1081 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
( ) ^ν_IN− ^{= V}_IN− ^sin(2πft)
The maximum voltage variation is determined by:
( ) ^max
dν_IN−
dt
=
V_IN−
2πf ≤ ^1LSB
t_CONV
=
V_REF
2¹⁰ t_CONV
A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / f_SCLK). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
C_HOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
C_HOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to V_DD1/2 within the limits of 10-bit resolu-
tion. This action is equivalent to transferring a
12pF ✕ [(V_IN+ - V_IN-)] charge from C_HOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
CS ¹⁷
SCLK ¹⁸
DIN ¹⁶
SHDN ¹⁰
CH0 ¹
CH1 ²
CH2 ³
CH3 ⁴
CH4 ⁵
CH5 ⁶
CH6 ⁷
CH7 ⁸
COM ⁹
REFADJ ¹²
REF ¹¹
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
ANALOG
INPUT
MUX
OUTPUT
SHIFT
REGISTER
T/H
CLOCK
IN
10 + 2-BIT
SAR ADC
OUT
REF
+1.22V
REFERENCE
A ≈ 2.05
17k
+2.500V
MAX1080
MAX1081
14 _DOUT
15 _SSTRB
20 _VDD1
19 _VDD2
13 _GND
GND
CAPACITIVE
REF
DAC
INPUT
CH0
MUX
CH1
C_HOLD
12pF
ZERO
COMPARATOR
CH2
CH3
C_SWITCH*
CH4
6pF
R_IN
800Ω
CH5
TRACK
CH6
HOLD
AT THE SAMPLING INSTANT,
CH7
THE MUX INPUT SWITCHES FROM
COM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
V_DD1/2
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
*INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit
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