MAX15046_10 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – 40V, High-Performance, Synchronous Buck Controller

40V, High-Performance, Synchronous
Buck Controller
VOUT
RI
R1
CI
R2
VREF
CCF
RF
CF
gM
COMP
Figure 4. Type III Compensation Network
overall thermal budget. Ensure that the DL gate driver
can drive the low-side MOSFET. In particular, check
that the dv/dt caused by the high-side MOSFET turning
on does not pull up the low-side MOSFET gate through
the drain-to-gate capacitance of the low-side MOSFET,
which is the most frequent cause of crossconduction
problems.
Check power dissipation when using the internal linear
regulator to power the gate drivers. Select MOSFETs
with low gate charge so that VCC can power both drivers
without overheating the device:
PDRIVE = VCC x QG_TOTAL x fSW
where QG_TOTAL is the sum of the gate charges of the
two external MOSFETs.
Boost Capacitor and Diode Selection
The MAX15046 uses a bootstrap circuit to generate
the necessary gate-to-source voltage to turn on the
high-side MOSFET. The selected n-channel high-side
MOSFET determines the appropriate boost capacitance
value (CBST in the Typical Application Circuits) accord-
ing to the following equation:
C_BST
=
QG
∆V_BST
where QG is the total gate charge of the high-side
MOSFET and DVBST is the voltage variation allowed
on the high-side MOSFET driver after turn-on. Choose
DVBST such that the available gate-drive voltage is not
significantly degraded (e.g. DVBST = 100mV to 300mV)
when determining CBST.
Use a low-ESR ceramic capacitor as the boost capacitor
with a minimum value of 100nF.
A small-signal diode can be used for the bootstrap cir-
cuit and must have a minimum voltage rating of VIN +
3V to withstand the maximum BST voltage. The average
forward current of the diode should meet the following
requirement:
IF > QGATE x fSW
where QGATE is the gate charges of the low-side MOSFET.
Power Dissipation
The maximum power dissipation of the device depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB copper
area, other thermal mass, and airflow.
The power dissipated into the package (PT) depends
on the supply configuration (see the Typical Application
Circuits). Use the following equation to calculate power
dissipation:
PT = VIN x [QG_TOTAL x fSW + IQ]
where IQ is the quiescent supply current at the switching
frequency. See the IIN vs. Switching Frequency graph in
the Typical Operating Characteristics for the IQ.
Use the following equation to estimate the temperature
rise of the die:
TJ = TA + (PT x BJA)
where BJA is the junction-to-ambient thermal impedance
of the package, PT is power dissipated in the device,
and TA is the ambient temperature. The BJA is 103.7NC/W
for the 16-pin QSOP and 44NC/W for the 16-pin QSOP-
EP package on multilayer boards, with the conditions
specified by the respective JEDEC standards (JESD51-5,
JESD51-7). An accurate estimation of the junction tem-
perature requires a direct measurement of the case
temperature (TC) when actual operating conditions
significantly deviate from those described in the JEDEC
standards. The junction temperature is then:
TJ = TC + (PT x BJC)
Use 37NC/W as BJC thermal impedance for the 16-pin
QSOP package and 6NC/W for the 16-pin QSOP-EP
package. The case-to-ambient thermal impedance (BCA)
is dependent on how well the heat is transferred from the
PCB to the ambient. Use large copper areas to keep the
PCB temperature low.
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