MAX15046_10 Datasheet, PDF (18/24 Pages) Maxim Integrated Products – 40V, High-Performance, Synchronous Buck Controller

40V, High-Performance, Synchronous
Buck Controller
So:
Once fP2 is known, calculate RI:
C_F
=
2π
× R_F
1
× 0.8
×
f_PO
2) The gain of the modulator (GAINMOD), comprised of
the pulse-width modulator, LC filter, feedback divider,
and associated circuitry at crossover frequency is:
GAIN_MOD
=
V_IN
V_RAMP
×
(2π
×
f_O ) ²
1
× L _OUT
× C_OUT
R_I
=
2π
×
1
f_P2
×
C_I
4) Place the second zero (fZ2) at 0.2 x fO or at fPO,
whichever is lower and calculate R1 using the following
equation:
R₁ =
1
2π × f_Z2
× C_I
-
R_I
The gain of the error amplifier (GAINEA) in midband
frequencies is:
GAIN_EA = 2π × f_O × C_I × R_F
The total loop gain as the product of the modulator gain
and the error amplifier gain at fO is 1.
GAIN_MOD × GAIN_EA = 1
So :
V_IN
V_RAMP
×
(2π
×
f_O ) ²
1
× C_OUT
× L _OUT
×
2π
×
f_O
× C_I
× R_F
=1
Solving for C_I :
C_I
=
V_RAMP
×
(2π × f_O × L _OUT
V_IN × R_F
×
C_OUT )
3) Use the second pole (fP2) to cancel fZO when fPO < fO
< fZO < fSW/2. The frequency response of the loop gain
does not flatten out soon after the 0dB crossover, and
maintains -20dB/decade slope up to 1/2 of the switching
frequency. This is likely to occur if the output capacitor
is low-ESR tantalum. Set fP2 = fZO.
When using a ceramic capacitor, the capacitor ESR
zero (fZO) is likely to be located even above one half
of the switching frequency, fPO < fO < fSW/2 < fZO. In
this case, place the frequency of the second pole (fP2)
high enough in order not to significantly erode the phase
margin at the crossover frequency. For example, set fP2
at 5 x fO so that the contribution to phase loss at the
crossover frequency fO is only about 11N:
fP2 = 5 x fO
5) Place the third pole (fP3) at one half the switching
frequency and calculate CCF:
C _CF
=
C_F
(2π × 0.5 × f_SW × R_F
× C_F )
-1
6) Calculate R2 as:
R₂
=
V_FB
V_OUT − V_FB
× R₁
MOSFET Selection
The MAX15046 step-down controller drives two exter-
nal logic-level n-channel MOSFETs. The key selection
parameters to choose these MOSFETs include:
U On-resistance (RDS(ON))
U Maximum Drain-to-Source Voltage (VDS(MAX))
U Minimum Threshold Voltage (VTH(MIN))
U Total Gate Charge (QG)
U Reverse Transfer Capacitance (CRSS)
U Power Dissipation
The two n-channel MOSFETs must be a logic-level
type with guaranteed on-resistance specifications at
VGS = 4.5V. For maximum efficiency, choose a high-
side MOSFET that has conduction losses equal to the
switching losses at the typical input voltage. Ensure that
the conduction losses at minimum input voltage do not
exceed the MOSFET package thermal limits, or violate
the overall thermal budget. Also ensure that the conduc-
tion losses plus switching losses at the maximum input
voltage do not exceed package ratings or violate the
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