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MAX15046_10 Datasheet, PDF (17/24 Pages) Maxim Integrated Products – 40V, High-Performance, Synchronous Buck Controller
40V, High-Performance, Synchronous
Buck Controller
The total loop gain, which is the product of the modulator
gain and the error-amplifier gain at fO, is:
1) GAINMOD × GAINEA = 1
So :
VIN
VOSC
×
(2π
×
ESR
fO × L OUT )
×
VFB
VOUT
× gM
× RF
=
1
Solving for RF :
RF
=
VOSC × (2π × fO × L OUT ) × VOUT
VFB × VIN × gM × ESR
2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel one
of the LC poles):
fZ1 =
1
2π ×RF
× CF
= 0.75 × fPO
Solving for CF:
CF
=
2π
× RF
1
× fPO
× 0.75
3) Place a high-frequency pole at fP1 = 0.5 x fSW (to
attenuate the ripple at the switching frequency fSW)
and calculate CCF using the following equation:
C CF
=
π ×RF
1
× fSW
-1
CF
VOUT
R1
R2
VREF
gM
RF
CF
COMP
CCF
Type III Compensation Network
(See Figure 4)
When using a low-ESR tantalum or ceramic type, the
ESR-induced zero frequency is usually above the tar-
geted zero crossover frequency (fO). Use Type III com-
pensation. Type III compensation provides two zeros
and three poles at the following frequencies:
fZ1
=
2π
×
1
RF
×
CF
fZ2
=
2π
×
CI
1
× (R1
+
RI)
Two midband zeros (fZ1 and fZ2) cancel the pair of com-
plex poles introduced by the LC filter:
fP1 = 0
fP1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors:
fP2
=
2π
1
× RI
×
CI
Depending on the location of the ESR zero (fZO), use fP2
to cancel fZO, or to provide additional attenuation of the
high-frequency output ripple:
fP3
=
2π
× RF
1
× CF
CF
×
+
C CF
C CF
fP3 attenuates the high-frequency output ripple.
Place the zeros and poles such that the phase margin
peaks around fO.
Ensure that RF >> 2/gM and the parallel resistance of
R1, R2, and RI is greater than 1/gM. Otherwise, a 180N
phase shift is introduced to the response making the
loop unstable.
Use the following compensation procedures:
1) With RF >> 10kI, place the first zero (fZ1) at 0.8 x
fPO:
fZ1 =
1
2π ×RF
× CF
= 0.8 × fPO
Figure 3. Type II Compensation Network
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