MAX13171E Datasheet, PDF (18/38 Pages) Maxim Integrated Products – Multiprotocol, Pin-Selectable Data Interface Chipset

Multiprotocol, Pin-Selectable
Data Interface Chipset
MAX13173E Pin Description (continued)
PIN
NAME
FUNCTION
37
C1+
V_DD Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1µF ceramic capacitor
between C1+ and C1-.
38
V_DD
Charge-Pump Positive-Supply Output. Connect a 4.7µF ceramic capacitor from V_DD to ground
as close as possible to the device.
Exposed Pad. Internally connected to V_EE. Connect to a large V_EE plane to maximize thermal
—
EP
performance, not intended as an electrical connection point. Does not share the same plane as
the MAX13171E.
MAX13175E Pin Description
PIN
1, 38
2, 3
4, 5
6, 7
8
9, 10
11, 12
13, 18
14
15
16
17
19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
32
33
34
35
36
37
—
NAME
R1B
R1A
R2A
R2B
R2C
R3A
R3B
GND
R3C
V_L
V_EE
V_DD
V_CC
R4B
R4A
R5B
R5A
R6A
R6B
DCE/DTE
LATCH
M2
M1
M0
R1C
EP
FUNCTION
Load 1, Node B
Load 1, Node A
Load 2, Node A
Lode 2, Node B
Lode 2, Center Tap
Load 3, Node A
Lode 3, Node B
Ground
Lode 3, Center Tap
Logic-Supply Reference Input. V_L determines the voltage level of the logic interface.
Negative Supply Voltage. Bypass V_EE to GND with a 0.1µF capacitor. Connect to V_EE from the
MAX13173E.
Positive Supply Voltage. Bypass V_DD to GND with a 0.1µF capacitor. Connect to V_DD from the
MAX13173E.
Supply Voltage. Bypass V_CC to GND with a 0.1µF capacitor as close as possible to the device.
Load 4, Node B
Load 4, Node A
Load 5, Node B
Load 5, Node A
Load 6, Node A
Load 6, Node B
DCE/DTE Mode-Select Input
Latch Signal Input. When LATCH is low, the input latches are transparent. When LATCH is high,
the data at the mode-select inputs are latched.
Mode-Select Input 2
Mode-Select Input 1
Mode-Select Input 0
Load 1, Center Tap
Exposed Pad. Internally connected to V_EE. Connect to a large V_EE plane to maximize thermal
performance, not intended as an electrical connection point. If V_EE is powered from the
MAX13173E’s V_EE, planes can be shared.
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