MAX12557 Datasheet, PDF (18/28 Pages) Maxim Integrated Products – Dual, 65Msps, 14-Bit, IF/Baseband ADC

Dual, 65Msps, 14-Bit, IF/Baseband ADC
V_DD
CLKP
CLKN
GND
S_1H
10kΩ
MAX12557
10kΩ
S_2H
S_1L
10kΩ
DUTY-CYCLE
EQUALIZER
10kΩ
SWITCHES S_{1_} AND S_{2_} ARE OPEN
S_2L DURING POWER-DOWN MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S_{2_} ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 4. Siimplified Clock Input Circuit
select either one-half or one-fourth of the clock speed for
sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.
System Timing Requirements
Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sam-
pled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
Table 2. Clock-Divider Control Inputs
DIV4
0
0
1
1
DIV2
0
1
0
1
FUNCTION
Clock Divider Disabled
f_SAMPLE = f_CLK
Divide-by-Two Clock Divider
f_SAMPLE = f_CLK / 2
Divide-by-Four Clock Divider
f_SAMPLE = f_CLK / 4
Not Allowed
cuitry can be latched with the rising edge of the con-
version clock (CLKP - CLKN).
Data-Valid Output
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12557 output data changes on the
falling edge of DAV, and DAV rises once the output
data is valid. The falling edge of DAV is synchronized
to have a 5.4ns delay from the falling edge of the input
clock. Output data at D0A/B–D13A/B and DORA/B are
valid from 7ns before the rising edge of DAV to 7ns
after the rising edge of DAV.
DAV enters high impedance when the MAX12557 is
powered down (PD = OV_DD). DAV enters its high-
impedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.
DAV is capable of sinking and sourcing 600µA and has
three times the driving capabilities of D0A/B–D13A/B
and DORA/B. DAV is typically used to latch the
MAX12557 output data into an external digital back-end
circuit. Keep the capacitive load on DAV as low as possi-
ble (<15pF) to avoid large digital currents feeding back
into the analog portion of the MAX12557, thereby
degrading its dynamic performance. Buffering DAV
(V_{REF_P} - V_{REF_N}) x 2/3
(V_{REF_N} - V_{REF_P}) x 2/3
CLKN
CLKP
DAV
D0_–D13_
DOR
DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)
N+4 N+5
N+3
N - 3 _{N - 2 N - 1 N N + 1 N +2}
N+6
N+7
N+9
N+8
t_AD
t_DAV
t_CL
t_CH
t_SETUP
t_HOLD
N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
8.0 CLOCK-CYCLE DATA LATENCY
t_SETUP
t_HOLD
Figure 5. System Timing Diagram
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