MAX12557 Datasheet, PDF (14/28 Pages) Maxim Integrated Products – Dual, 65Msps, 14-Bit, IF/Baseband ADC

Dual, 65Msps, 14-Bit, IF/Baseband ADC
Pin Description (continued)
PIN
NAME
FUNCTION
Power-Down Digital Input.
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PD
PD = GND: ADCs are fully operational.
PD = OV_DD: ADCs are powered down.
Shared Reference Digital Input.
SHREF = V_DD: Shared reference enabled.
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SHREF
SHREF = GND: Shared reference disabled.
When sharing the reference, externally connect REFAP and REFBP together to ensure that V_REFAP =
V_REFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure
that V_REFAN = V_REFBN.
Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.
For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from
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REFOUT REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor.
For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥0.1µF
capacitor.
Single-Ended Reference Analog Input.
For internal reference and buffered external reference operation, apply a 0.7V to 2.3V DC reference
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REFIN
voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor. Within its specified operating voltage,
REFIN has a >50MΩ input impedance, and the differential reference voltage (V_{REF_P} - V_{REF_N}) is
generated from REFIN. For unbuffered external reference operation, connect REFIN to GND. In this
mode, REF_P, REF_N, and COM_ are high-impedance inputs that accept the external reference voltages.
—
EP
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified
dynamic performance.
MAX12557
FLASH
ADC
+_Σ
x2
−
DAC
IN_P
STAGE 10
IN_N
STAGE 1
STAGE 2
STAGE 9
END OF PIPELINE
DIGITAL ERROR CORRECTION
D0_ THROUGH D13_
Figure 1. Pipeline Architecture—Stage Blocks
Detailed Description
The MAX12557 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12557 functional diagram.
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