MAX12557 Datasheet, PDF (12/28 Pages) Maxim Integrated Products – Dual, 65Msps, 14-Bit, IF/Baseband ADC

Dual, 65Msps, 14-Bit, IF/Baseband ADC
Pin Description
PIN
1, 4, 5, 9,
13, 14, 17
2
3
6
7
8
10
11
12
15
16
18
19
20
21
22
23–26, 61,
62, 63
27, 43, 60
NAME
FUNCTION
GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
INAP
INAN
COMA
REFAP
REFAN
REFBN
REFBP
COMB
INBN
INBP
DIFFCLK/
SECLK
CLKN
CLKP
DIV2
DIV4
V_DD
OV_DD
Channel A Positive Analog Input
Channel A Negative Analog Input
Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V_REFAP - V_REFAN). Bypass
REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (V_REFAP - V_REFAN). Bypass
REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (V_REFBP - V_REFBN). Bypass
REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (V_REFBP - V_REFBN). Bypass
REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
Channel B Negative Analog Input
Channel B Positive Analog Input
Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
input drives.
DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
DIFFCLK/SECLK = OV_DD: Selects differential clock input drive.
Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV_DD), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the clock signal to CLKP and connect CLKN to GND.
Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV_DD), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the single-ended clock signal to CLKP and connect CLKN to GND.
Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
Analog Power Input. Connect V_DD to a 3.15V to 3.60V power supply. Bypass V_DD to GND with a parallel
capacitor combination of ≥10µF and 0.1µF. Connect all V_DD pins to the same potential.
Output-Driver Power Input. Connect OV_DD to a 1.7V to V_DD power supply. Bypass OV_DD to GND with a
parallel capacitor combination of ≥10µF and 0.1µF.
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