MAX1438B Datasheet, PDF (17/21 Pages) Maxim Integrated Products – Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs

Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0000 1011 1101. Drive LVDSTEST low for nor-
mal operation (test pattern disabled).
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DC-
coupled analog inputs. If the input is DC-coupled,
match the output common-mode voltage of the circuit
driving the MAX1438B to the output voltage at V_CMOUT
to within ±50mV. It is recommended that the output
common-mode voltage of the driving circuit be derived
from CMOUT.
Double Termination (DT)
The MAX1438B offers an optional, internal 100Ω termi-
nation between the differential output pairs (OUT_P and
OUT_N, CLKOUTP and CLKOUTN, FRAMEP and
FRAMEN). In addition to the termination at the end of
the line, a second termination directly at the outputs
helps eliminate unwanted reflections down the line. This
feature is useful in applications where trace lengths are
long (> 5in) or with mismatched impedance. Drive DT
high to select double-termination, or drive DT low to
disconnect the internal termination resistor (single-ter-
mination). Selecting double-termination increases the
OVDD supply current (see Figure 7).
Standby Mode
The MAX1438B offers a standby mode to efficiently use
power by transitioning to a low-power state when con-
versions are not required. STBY controls the standby
mode of all channels and the internal reference circuitry.
The reference does not power down in standby mode.
Drive STBY high to enable standby. In standby mode,
the output impedance of all of the LVDS/SLVS outputs is
approximately 342Ω, if DT is low. The output impedance
of the differential LVDS/SLVS outputs is 100Ω when DT
is high. See the Electrical Characteristics table for typi-
cal supply currents during standby. The following list
shows the state of the analog inputs and digital outputs
in standby mode:
• IN_P, IN_N analog inputs are disconnected from the
internal input amplifier.
• Reference circuit remains active.
• OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 342Ω between the
output pairs when DT is low. When DT is high, the dif-
ferential output pairs have 100Ω between each pair.
When operating in internal reference mode, the
MAX1438B requires 200µs to power up and settle when
DT
OUT_P/
CLKOUTP/
FRAMEP
Z₀ = 50Ω
100Ω
100Ω
MAX1438B
OUT_N/
CLKOUTN/
FRAMEN
Z₀ = 50Ω
SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.
Figure 7. Double Termination
the converter exits standby mode. To exit standby mode,
STBY, the applied control signal must transition from
high to low. When using an external reference, the wake-
up time is dependent on the external reference drivers.
Applications Information
Full-Scale Range Adjustments
Using the Internal Reference
The MAX1438B supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, add a 25kΩ
to 250kΩ external resistor or potentiometer (R_ADJ) between
REFADJ and GND. To increase the full-scale range, add a
25kΩ to 250kΩ resistor between REFADJ and REFIO.
Figure 8 shows the two possible configurations.
The following equations provide the relationship between
R_ADJ and the change in the analog full-scale range:
FSR
=
0.7V
⎛
⎝⎜¹
+
1.25kΩ ⎞
R_ADJ ⎠⎟
for R_ADJ connected between REFADJ and REFIO, and:
FSR
=
0.7V
⎛
⎝⎜¹
−
1.25kΩ ⎞
R_ADJ ⎠⎟
for R_ADJ connected between REFADJ and GND.
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