MAX1438B Datasheet, PDF (10/21 Pages) Maxim Integrated Products – Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs

Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
Pin Description
PIN
1
2
3
4
5
6
7, 8, 10, 11,
25, 26, 27, 60
9, 18, 68
12
13
14
15
16
17
19
20
21
22
23
24
28, 31, 34, 39,
44, 49, 52
29
30
32
33
35
36
37
38
40
41
42
NAME
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
AVDD
GND
IN4P
IN4N
IN5P
IN5N
IN6P
IN6N
IN7P
IN7N
DT
SLVS/LVDS
CVDD
CLK
OVDD
OUT7N
OUT7P
OUT6N
OUT6P
OUT5N
OUT5P
OUT4N
OUT4P
FRAMEN
FRAMEP
CLKOUTN
FUNCTION
Channel 1 Positive Input
Channel 1 Negative Input
Channel 2 Positive Input
Channel 2 Negative Input
Channel 3 Positive Input
Channel 3 Negative Input
Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass AVDD to GND with a
0.1µF capacitor as close as possible to the device. Bypass the AVDD power plane to the GND plane
with a bulk capacitor of at least 2.2µF. Connect all AVDD pins to the same potential.
Ground. Connect all GND pins to the same potential.
Channel 4 Positive Input
Channel 4 Negative Input
Channel 5 Positive Input
Channel 5 Negative Input
Channel 6 Positive Input
Channel 6 Negative Input
Channel 7 Positive Input
Channel 7 Negative Input
Double Termination Select. Force DT high to select the internal 100Ω termination between the
differential output pairs. Force DT low to select no internal output termination.
Differential Output Signal Format Select Input. Force SLVS/LVDS high to select SLVS outputs. Force
SLVS/LVDS low to select LVDS outputs.
Clock Power Input. Connect CVDD to a 1.7V to 3.5V supply. Bypass CVDD to GND with a 0.1µF
capacitor in parallel with a capacitor of at least 2.2µF. Install the bypass capacitors as close as
possible to the device. CVDD is used to bias ESD-protection diodes on CLK (see Figure 2).
Single-Ended CMOS Clock Input
Output Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass OVDD to GND
with a 0.1µF capacitor as close as possible to the device. Bypass the OVDD power plane to the
GND plane with a bulk capacitor of at least 2.2µF. Connect all OVDD pins to the same potential.
Channel 7 Negative LVDS/SLVS Output
Channel 7 Positive LVDS/SLVS Output
Channel 6 Negative LVDS/SLVS Output
Channel 6 Positive LVDS/SLVS Output
Channel 5 Negative LVDS/SLVS Output
Channel 5 Positive LVDS/SLVS Output
Channel 4 Negative LVDS/SLVS Output
Channel 4 Positive LVDS/SLVS Output
Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.
Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.
Negative LVDS/SLVS Serial Clock Output
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