MAX1438 Datasheet, PDF (17/22 Pages) Maxim Integrated Products – Octal, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Serial LVDS Outputs

Octal, 12-Bit, 65Msps, 1.8V ADC
with Serial LVDS Outputs
LVDS and SLVS Signals (SLVS/LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high
for SLVS levels at the MAX1438 outputs (OUT_P, OUT_N,
CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For
SLVS levels, enable double-termination by driving DT
high. See the Electrical Characteristics table for LVDS
and SLVS output voltage levels.
DT
OUT_P/
CLKOUTP/
FRAMEP
Z₀ = 50Ω
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0000 1011 1101. Drive LVDSTEST low for
100Ω
100Ω
normal operation (test pattern disabled).
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DC-
coupled analog inputs. If the input is DC-coupled,
match the output common-mode voltage of the circuit
driving the MAX1438 to the output voltage at V_CMOUT
to within ±50mV. It is recommended that the output
common-mode voltage of the driving circuit be derived
from CMOUT.
Double-Termination (DT)
The MAX1438 offers an optional, internal 100Ω termination
between the differential output pairs (OUT_P and OUT_N,
CLKOUTP and CLKOUTN, FRAMEP and FRAMEN).
In addition to the termination at the end of the line, a
second termination directly at the outputs helps eliminate
unwanted reflections down the line. This feature is useful
in applications where trace lengths are long (>5in) or with
mismatched impedance. Drive DT high to select double-
termination, or drive DT low to disconnect the internal ter-
mination resistor (single-termination). Selecting
double-termination increases the OVDD supply current
(see Figure 8).
Power-Down Mode (PD)
The MAX1438 offers a power-down mode to efficiently
use power by transitioning to a low-power state when
conversions are not required.
PD controls the power-down mode of all channels and
the internal reference circuitry. Drive PD high to enable
power-down. In power-down mode, the output imped-
ance of all of the LVDS/SLVS outputs is approximately
342Ω, if DT is low. The output impedance of the differen-
tial LVDS/SLVS outputs is 100Ω when DT is high. See the
Electrical Characteristics table for typical supply currents
during power-down. The following list shows the state of
the analog inputs and digital outputs in power-down
mode:
• IN_P, IN_N analog inputs are disconnected from
the internal input amplifier
• REFIO has > 1MΩ to GND
MAX1438
OUT_N/
CLKOUTN/
FRAMEN
Z₀ = 50Ω
SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.
Figure 8. Double-Termination
• OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 342Ω between
the output pairs when DT is low. When DT is high,
the differential output pairs have 100Ω between
each pair.
When operating from the internal reference, the wake-
up time from power-down is typically 100ms (C_REFP to
GND = C_REFN to GND = 1µF). When using an external
reference, the wake-up time is dependent on the exter-
nal reference drivers.
Applications Information
Full-Scale Range Adjustments
Using the Internal Reference
The MAX1438 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, add a
25kΩ to 250kΩ external resistor or potentiometer (R_ADJ)
between REFADJ and GND. To increase the full-scale
range, add a 25kΩ to 250kΩ resistor between REFADJ
and REFIO. Figure 9 shows the two possible configura-
tions.
The following equations provide the relationship between
R_ADJ and the change in the analog full-scale range:
FSR
=
⎛
0.7V_⎝⎜1 +
1.25kΩ
R_ADJ
⎞
⎠⎟
for R_ADJ connected between REFADJ and REFIO, and:
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