MAX1438 Datasheet, PDF (15/22 Pages) Maxim Integrated Products – Octal, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Serial LVDS Outputs

Octal, 12-Bit, 65Msps, 1.8V ADC
with Serial LVDS Outputs
N
(V_{IN_P} -
V_{IN_N})
N+1
t_SAMPLE
CLK
N+2
N+3
N+5
N+4
6.5 CLOCK-CYCLE DATA LATENCY
(V_FRAMEP -
V_FRAMEN)*
(V_CLKOUTP -
V_CLKOUTN)
(V_{OUT_P} -
V_{OUT_N})
OUTPUT
DATA FOR
SAMPLE
N-6
*DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY.
Figure 3. Global Timing Diagram
N+6
N+9
N+8
N+7
OUTPUT
DATA FOR
SAMPLE N
N
(V_{IN_P} - V_{IN_N})
N+2
N+1
t_SAMPLE
t_SF
CLK
(V_FRAMEP -
V_FRAMEN)*
t_CF
(V_CLKOUTP -
V_CLKOUTN)
(V_{OUT_P} -
V_{OUT_N})
D5_N-7 D6_N-7 D7_N-7 D8_N-7 D9_N-7 D10_N-7 D11_N-7 D0_N-6 D1_N-6 D2_N-6 D3_N-6 D4_N-6 D5_N-6 D6_N-6 D7_N-6 D8_N-6 D9_N-6 D10_N-6 D11_N-6 D0_N-5 D1_N-5 D2_N-5 D3_N-5 D4_N-5 D5_N-5 D6_N-5
*DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY.
Figure 4. Detailed Two-Conversion Timing Diagram
t_CH
t_CL
(V_CLKOUTP -
V_CLKOUTN)
t_OD
t_OD
(V_{OUT_P} -
V_{OUT_N})
D0
D1
D2
D3
Figure 5. Serialized-Output Detailed Timing Diagram
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