MAX1206 Datasheet, PDF(17/29 Page) Maxim Integrated Products

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MAX1206 Datasheet, PDF (17/29 Pages) Maxim Integrated Products – 40Msps, 12-Bit ADC

◁

40Msps, 12-Bit ADC

Detailed Description

The MAX1206 uses a 10-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half clock cycle.

From input to output, the total clock-cycle latency is 8.5

clock cycles.

Each pipeline converter stage converts its input voltage

into a digital output code. At every stage, except the

last, the error between the input voltage and the digital

output code is multiplied and passed along to the next

pipeline stage. Digital error correction compensates for

ADC comparator offsets in each pipeline stage and

ensures no missing codes. Figure 2 shows the

MAX1206 functional diagram.

Input Track-and-Hold (T/H) Circuit

Figure 3 displays a simplified functional diagram of the

input T/H circuits. In track mode, switches S1, S2a,

S2b, S4a, S4b, S5a, and S5b are closed. The fully dif-

ferential circuits sample the input signals onto the two

capacitors (C2a and C2b) through switches S4a and

S4b. S2a and S2b set the common mode for the opera-

tional transconductance amplifier (OTA), and open

simultaneously with S1, sampling the input waveform.

Switches S4a, S4b, S5a, and S5b are then opened

before switches S3a and S3b connect capacitors C1a

and C1b to the output of the amplifier and switch S4c is

closed. The resulting differential voltages are held on

capacitors C2a and C2b. The amplifiers charge capac-

itors C1a and C1b to the same values originally held on

T/H

FLASH

ADC

DAC

1.5 BITS

INP

T/H

INN

STAGE 1

GAIN OF 8

STAGE 2

GAIN OF 2

STAGE 9

GAIN OF 2

STAGE 10

END OF PIPE

4 BITS

1.5 BITS

1 BIT

DIGITAL ERROR CORRECTION

D0âD11

C2a and C2b. These values are then presented to the

first-stage quantizers and isolate the pipelines from the

fast-changing inputs. The wide input-bandwidth T/H

amplifier allows the MAX1206 to track and sample/hold

analog inputs of high frequencies well beyond Nyquist.

Analog input INP to INN can be driven either differen-

tially or single ended. For differential inputs, balance

the input impedance of INP and INN and set the com-

mon-mode voltage to midsupply (VDD / 2) for optimum

performance.

CLKP

CLKN

DCE

CLKTYP

INP

INN

REFOUT

REFIN

REFP

COM

REFN

CLOCK

GENERATOR

AND

DUTY-CYCLE

EQUALIZER

12-BIT

T/H

PIPELINE

ADC

MAX1206

DEC

OUTPUT

DRIVERS

REFERENCE

SYSTEM

POWER CONTROL

AND

BIAS CIRCUITS

VDD

GND

OVDD

D0âD11

DAV

DOR

G/T

Figure 2. Functional Diagram

SWITCHES SHOWN IN TRACK MODE

INTERNAL

BIAS

CML

MAX1206

S2a

C1a S5a

VDD

S4a

C2a

S3a

INP

OUT

S4c

OTA

OUT

INN

S4b

C2b

C1b

GND

S3b

S2b

S5b

INTERNAL

CML

BIAS

Figure 1. Pipeline ArchitectureâStage Blocks

Figure 3. Internal T/H Circuit

______________________________________________________________________________________ 17

▷