MAX1206 Datasheet, PDF (15/29 Pages) Maxim Integrated Products – 40Msps, 12-Bit ADC

40Msps, 12-Bit ADC
Typical Operating Characteristics (continued)
(V_DD = 3.3V, OV_DD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C_REFOUT = 0.1µF, C_L ≈ 5pF at digital outputs, V_IN = -0.5dBFS
differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, f_CLK = 40MHz (50% duty cycle), C_REFP = C_REFN = 0.1µF to GND, 1µF
in parallel with 10µF between REFP and REFN, C_COM = 0.1µF in parallel with 2.2µF to GND, T_A = +25°C, unless otherwise noted.)
OFFSET ERROR
vs. TEMPERATURE
-0.12
V_REFIN = 2.048V
-0.14
-0.16
-0.18
-0.20
-0.22
-0.24
-0.26
-0.28
-40 -15
10
35
60
85
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
1.0
0.9 ^{VREFIN = 2.048V}
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40 -15
10
35
60
85
TEMPERATURE (°C)
PIN
1
2
3
4, 7, 16, 35
5
6
8
9
10
Pin Description
NAME
REFP
REFN
COM
GND
INP
INN
DCE
CLKN
CLKP
FUNCTION
Positive Reference I/O. Conversion range is ±(V_REFP - V_REFN). Bypass REFP to GND with a 0.1µF
capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN.
Negative Reference I/O. Conversion range is ±(V_REFP - V_REFN). Bypass REFN to GND with a 0.1µF
capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN.
Common-Mode Voltage I/O. Bypass COM to GND with a ≥2.2µF capacitor in parallel with a 0.1µF
capacitor.
Ground. Connect all ground pins and the EP together.
Positive Analog Input. For single-ended input operation, connect signal source to INP and connect INN
to COM. For differential operation, connect the input signal between INP and INN.
Negative Analog Input. For single-ended input operation, connect INN to COM. For differential operation,
connect the input signal between INP and INN.
Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OV_DD or DV_DD) to enable the internal duty-cycle equalizer.
Negative Clock Input. In differential clock input mode (CLKTYP = OV_DD or V_DD), connect the clock
signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the clock signal
to CLKP and tie CLKN to GND.
Positive Clock Input. In differential clock input mode (CLKTYP = OV_DD or V_DD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
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