MAX16070 Datasheet, PDF (13/52 Pages) Maxim Integrated Products – 12-Channel/8-Channel, Flash-Configurable System Monitors with Nonvolatile Fault Registers

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Boot-Up Delay
Once EN is above its threshold and the software-enable
bit is set, a boot-up delay occurs before monitoring
begins. This delay is configured in register r77h[3:0] as
shown in Tables 2 and 3.
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a current-
sense amplifier facilitate power monitoring (see Figure
4). The voltage on CSP relative to GND is also monitored
by the ADC when the current-sense amplifier is enabled
with r47h[0]. The conversion results are located in regis-
ters r19h and r1Ah (see Table 6). There are two select-
able voltage ranges for CSP set by r47h[1], see Table
4. Although the voltage can be monitored over SMBus
or JTAG, this voltage has no threshold comparators and
cannot trigger any faults. Regarding the current-sense
amplifier, there are four selectable ranges and the ADC
output for a current-sense conversion is:
XADC = (VSENSE x AV)/1.4V x (2⁸ - 1)
where XADC is the 8-bit decimal ADC result in register
r18h, VSENSE is VCSP - VCSM, and AV is the current-
sense voltage gain set by r47h[3:2].
In addition, there are two programmable current-sense
trip thresholds: primary overcurrent and secondary over-
current. For fast fault detection, the primary overcurrent
threshold is implemented with an analog comparator
connected to the internal OVERC signal. The OVERC
signal can be output on one of the GPIO_s. See the
General-Purpose Inputs/Outputs section for configur-
ing the GPIO_ to output the OVERC signal. The primary
threshold is set by:
ITH = VCSTH/RSENSE
where ITH is the current threshold to be set, VCSTH is
the threshold set by r47h[3:2], and R_SENSE is the value
of the sense resistor. See Table 4 for a description of
r47h. OVERC depends only on the primary overcurrent
threshold. The secondary overcurrent threshold is imple-
mented through ADC conversions and digital compari-
son set by r6Ch. The secondary overcurrent threshold
includes programmable time delay options located in
r73h[6:5]. Primary and secondary current-sense faults
are enabled/disabled through r47h[0].
Table 2. Boot-Up Delay Register
REGISTER
ADDRESS
77h
FLASH
ADDRESS
277h
BIT RANGE
[3:0]
[7:0]
Boot-up delay
Reserved
DESCRIPTION
Table 3. Boot-Up Delay Values
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VALUE
25Fs
500Fs
1ms
2ms
3ms
4ms
6ms
8ms
10ms
12ms
25ms
100ms
200ms
400ms
800ms
1.6s
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