MAX15096 Datasheet, PDF (12/15 Pages) Maxim Integrated Products – Integrated Hot-Swap/Electronic

MAX15096/MAX15096A/
MAX15096D
2.7V to 18V, 6A Integrated Hot-Swap/
Electronic Circuit Breaker
Circuit-Breaker Comparator
and Current Limit
The current through the internal power MOSFET is com-
pared to a circuit-breaker threshold. An external resistor
between CB and ground sets this threshold according to
the following formula:
I_CB = (R_CB/6501)(A/Ω) - 0.34A
where I_CB is in amps and R_CB (the resistor between CB
and ground) is in ohms.
The circuit-breaker comparator is designed so that the
load current can exceed the threshold for some amount
of time before tripping. The time delay varies inversely
with the overdrive above the threshold. The greater the
overcurrent condition, the faster the response time,
allowing the devices to tolerate load transients and noise
near the circuit-breaker threshold. The maximum allowed
external resistor value is 41.2kΩ, which corresponds to a
6A CB threshold setting. Programming the CB threshold
to a value higher than 6A could cause unsafe operating
conditions, resulting in damage to the device.
The devices also feature catastrophic short-circuit
protection. During normal operation, if OUT is shorted
directly to ground, a fast protection circuit forces the
gate of the internal MOSFET to discharge quickly and
disconnect the output from the input.
Autoretry and Latchoff Fault Management
During a fault condition, the devices turn off the internal
MOSFET, disconnecting the output from the input. The
MAX15096A enters an autoretry mode and restarts after
t_RESTART (3.4s typ.) time delay elapses.
The MAX15096 latches off and remains off until the
enable logic is cycled off and on after a certain delay. The
delay prevents the latchoff device to restart and operate
with unsafe power-dissipation duty cycle. See the Timing
diagram and Table 1 for delay values.
Latchoff Reset
The latchoff could be reset if any one of the following
happens:
● V_CC is below its UVLO threshold
● EN is disabled for longer than 100μs
● UV is triggered
● PRSNT goes above its threshold
● OV is triggered
Power-Good (PG) Delay
The devices feature an open-drain, power-good output
that asserts after t_PG delay, indicating that OUT voltage
has reached (0.9 x V_IN) voltage and (V_GATE - V_OUT) > 3V.
REG
The devices include a linear regulator that outputs 3.3V
at REG. REG provides power to the internal circuit blocks
of the devices and must not be loaded externally (except
a resistor > 50kΩ connected from REG to EN). REG
requires a 1µF capacitor to ground for proper operation.
Output Discharging
The discharge FET is active when the output is disabled
or under fault event. In this event, the hot-swap is off
and the output is on the way down. The discharging is
triggered after the main FET has completely turned off.
The maximum output capacitance is approximately
1000µF. The voltage could be up to 18V. Ideally, it
discharges the output capacitor in constant power mode
(710mW typ) to ensure the voltage rail is below 0.3V
within 2s or less time.
TIMER
Connect a resistor from the TIMER pin to the GND pin to
program the fast-trip response time. This time is the sum
of the internal fast-comparator propagation delay (less
than 200ns typ) plus an additional delay set by the exter-
nal resistor connected from TIMER to ground. Choosing
different resistance values, it is possible to change the
value of additional delay. If the TIMER pin is connected
to REG, the total response time is less than 200ns (typ).
Additional delay is disabled also during the startup phase
or after a short-circuit event (V_OUT < 90% V_IN). Be careful
about additional delay settings related to a short event.
Additional delay can be calculated using the following
formula:
Additional_Delay (µs) = R_TIMER (kΩ) x 22.9E^-03
Maximum additional delay time is set to 2µs. Table 3 pro-
vides additional delay settings.
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