88F6190_1 Datasheet, PDF (47/150 Pages) –

2.2.15 Audio (S/PDIF / I²S) Interface
Pin and Signal Descriptions
Pin Descriptions
Note
„ The Audio interface is only relevant for the 88F6192.
„ All of the Audio signals are multiplexed on the MPP pins (see Section 6, Pin
Multiplexing, on page 61).
„ If the Audio interface is not used, leave all of the signals unconnected.
„ The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin
multiplexing option.
Table 19: Audio (S/PDIF / I²S) Interface Signal Assignment
Pin Name
I/O Pin
Ty p e
Power
Rail
Description
AU_SPDIFI
I
CMOS
VDD_GE_B S/PDIF In
AU_SPDIFO
AU_
SPDFRMCLK
AU_I2SBCLK
AU_I2SDO
AU_I2SLRCLK
AU_I2SMCLK
AU_I2SDI
O CMOS
O CMOS
O CMOS
O CMOS
O CMOS
O CMOS
I
CMOS
VDD_GE_B
VDD_GE_B
VDD_GE_B
VDD_GE_B
VDD_GE_B
VDD_GE_B
VDD_GE_B
S/PDIF Out
S/PDIF Recovered Master Clock (256 x F_s)¹
For the frequency of this clock, see the Audio External
Reference Clock section of Table 51, Reference Clock AC
Timing Specifications, on page 97.
I²S Bit Clock (64 x F_s)
Transmitter Data Out
I²S Left/Right Clock (1 x F_s)
I²S Master Clock (256 x F_s)
I²S Receiver Data In
AU_EXTCLK
I
CMOS
VDD_GE_B External Audio Clock
For the frequency of this clock, see the Audio External
Reference Clock section of Table 51, Reference Clock AC
Timing Specifications, on page 97.
1. F_s is the audio sample rate.
Copyright © 2008 Marvell
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F
Page 47