88F6190_1 Datasheet, PDF (18/150 Pages) –

88F619x
Hardware Specifications
1
Overview
The Marvell^® 88F6190 and 88F6192 devices are high-performance, highly integrated controllers.
The devices are based on the ARMv5TE-compliant, high-speed Sheeva^™ 88SV131 CPU core with
256 KB L2 cache.
Table 1 provides a list of the differences between the 88F6190 and 88F6192 devices.
Table 1: 88F6190 and 88F6192 Device Differences
Sheeva^™ CPU Core
Time Division
Multiplexing
(SLIC/codec) Interface
Serial ATA II (SATA II)
Interface
Gigabit Ethernet
Interface
Audio S/PDIF / I2S
Interface
MPEG Video / Transport
Stream Interface (TS)
DDR SDRAM Interface
PCI Express Interface
USB 2.0 Interface
Cryptographic Engine
and Security
Accelerator
XOR engine and DMA
Two-Wire Serial
Interface (TWSI)
UART Interface
NAND Flash Interface
SPI Serial Flash
Interface
SDIO Interface
88F6190
Running at up to 600 MHz
L2 cache at up to 300 MHz
No
88F6192
Running at up to 800 MHz
L2 cache at up to 400 MHz
Yes¹
1 port
2 ports
2 Ethernet ports
• Port0 RGMII, Port1 MII/MMII
• Port0 GMII, Port1 N/A
No
2 Ethernet ports¹
• Port0 RGMII, Port1 RGMII
• Port0 RGMII, Port1 MII/MMII
• Port0 MII/MMII, Port1 RGMII
• Port0 GMII, Port1 N/A
Yes¹
No
Yes¹
• Up to 200 MHz clock frequency with an 400 MHz data rate
• Supports two DRAM chip selects
• Supports all DDR devices densities up to 1Gb
• Supports up to 16 open pages (page per bank)
• Up to 512 MB total address space
Yes
Yes
Yes
Yes
1 port
2 ports
Yes
Yes
Yes
Doc. No. MV-S104987-U0 Rev. F
Page 18
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary