88F6190_1 Datasheet, PDF (108/150 Pages) –

88F619x
Hardware Specifications
10.6.6 Serial Management Interface (SMI) AC Timing
10.6.6.1 SMI Master Mode AC Timing Table
Table 57: SMI Master Mode AC Timing Table
De s cr iption
MDC clock frequency
MDC clock duty cycle
MDIO input setup time relative to MDC rise time
MDIO input hold time relative to MDC rise time
MDIO output valid before MDC rise time
MDIO output valid after MDC rise time
Sym bol
f CK
tDC
tSU
tHO
tOVB
tOVA
M in
M ax
See note 2
0.4
0.6
40.0
-
0.0
-
15.0
-
15.0
-
Units
MHz
tCK
ns
ns
ns
ns
Note s
2
-
-
-
1
1
Note s :
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF.
2. See "Reference Clocks" table for more details.
10.6.6.2
SMI Master Mode Test Circuit
Figure 20: MDIO Master Mode Test Circuit
VDDIO
Test Point
2 kilohm
MDIO
CL
Doc. No. MV-S104987-U0 Rev. F
Page 108
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary