88F6190_1 Datasheet, PDF (14/150 Pages) –

88F619x
Hardware Specifications
List of Figures
1 Overview........................................................................................................................................... 18
2 Pin and Signal Descriptions ........................................................................................................... 20
Figure 1: 88F6190 Pin Logic Diagram .............................................................................................................21
Figure 2: 88F6192 Pin Logic Diagram .............................................................................................................22
3 Unused Interface Strapping............................................................................................................ 56
4 88F6190 Pinout ................................................................................................................................ 57
Figure 3: 88F6190 Pin Map Top View .............................................................................................................57
5 88F6192 Pinout ................................................................................................................................ 59
Figure 4: 88F6192 Pin Map Top View .............................................................................................................59
6 Pin Multiplexing ............................................................................................................................... 61
7 Clocking............................................................................................................................................ 71
8 System Power Up/Down and Reset Settings ................................................................................ 73
Figure 5: Power-Up Sequence Example..........................................................................................................74
Figure 6: Serial ROM Data Structure ...............................................................................................................80
Figure 7: Serial ROM Read Example...............................................................................................................81
9 JTAG Interface ................................................................................................................................. 83
10 Electrical Specifications (Preliminary) .......................................................................................... 85
Figure 8: SDRAM DDR2 Interface Test Circuit ..............................................................................................100
Figure 9: SDRAM DDR2 Interface Write AC Timing Diagram .......................................................................100
Figure 10: SDRAM DDR2 Interface Address and Control AC Timing Diagram ...............................................101
Figure 11: SDRAM DDR2 Interface Read AC Timing Diagram .......................................................................101
Figure 12: RGMII Test Circuit ..........................................................................................................................103
Figure 13: RGMII AC Timing Diagram .............................................................................................................103
Figure 14: GMII Test Circuit .............................................................................................................................104
Figure 15: GMII Output AC Timing Diagram ....................................................................................................105
Figure 16: GMII Input AC Timing Diagram.......................................................................................................105
Figure 17: MII/MMII MAC Mode Test Circuit....................................................................................................106
Figure 18: MII/MMII MAC Mode Output Delay AC Timing Diagram.................................................................106
Figure 19: MII/MMII MAC Mode Input AC Timing Diagram..............................................................................107
Figure 20: MDIO Master Mode Test Circuit .....................................................................................................108
Figure 21: MDC Master Mode Test Circuit ......................................................................................................109
Figure 22: SMI Master Mode Output AC Timing Diagram ...............................................................................109
Figure 23: SMI Master Mode Input AC Timing Diagram ..................................................................................109
Figure 24: JTAG Interface Test Circuit ............................................................................................................110
Doc. No. MV-S104987-U0 Rev. F
Page 14
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary