28953-DSH-001-A Datasheet, PDF (86/173 Pages) M/A-COM Technology Solutions, Inc. – HDSL Channel Unit

4.0 Registers
4.4 HDSL Receive
RS8953B/8953SPB
HDSL Channel Unit
4.4 HDSL Receive
Base Address
HDSL Channel 1
(CH1)
0x60
HDSL Channel 2
(CH2)
0x80
HDSL Channel 3
(CH3)
0xA0
Table 4-3. HDSL Receive Write Registers
CH1 CH2 CH3
Register Label
Bits
0x60 0x80 0xA0
RCMD_1
8
0x61 0x81 0xA1
RCMD_2
8
0x62 0x82 0xA2
RFIFO_RST
–
0x63 0x83 0xA3
SYNC_RST
–
0x64 0x84 0xA4
RMAP_1
6
0x65 0x85 0xA5
RMAP_2
6
0x66 0x86 0xA6
RMAP_3
6
0x67 0x87 0xA7
RMAP_4
6
0x68 0x88 0xA8
RMAP_5
6
0x69 0x89 0xA9
RMAP_6
6
0x70 0x70 0xA0
ERR_RST
–
0x71 0x71 0xA1
RSIG_LOC
4
Name/Description
Configuration
Configuration
Receive FIFO Reset
Receive Framer Reset
Payload Map
Payload Map
Payload Map
Payload Map
Payload Map
Payload Map
Error Count Reset
Receive Signaling Location
Three identical groups of write-only registers configure the HDSL receivers, and control the mapping of HDSL
payload bytes into the receiver elastic stores (RFIFO). Configuration registers define each HDSL receive
framer’s criteria for loss and recovery of frame alignment by selecting the number of detected SYNC word
errors used to declare loss of sync or needed to acquire sync. Refer to the Framer Synchronization State
Diagram, Figure 3-23. Frame alignment criteria are programmable to meet different standard application
requirements.
4-18
Conexant
N8953BDSB