28953-DSH-001-A Datasheet, PDF (100/173 Pages) M/A-COM Technology Solutions, Inc. – HDSL Channel Unit

4.0 Registers
4.8 Transmit Bit Stuffing Thresholds
0xCE—RX FIFO Water Level (RFIFO_WL_HI)
RS8953B/8953SPB
HDSL Channel Unit
7
6
5
4
3
2
—
—
—
—
—
—
1
0
RFIFO_WL[9:8]
RFIFO_WL[8:0]
Receive FIFO Water Level—Sets the RCLK bit delay from the master HDSL channel’s receive
6 ms frame to the PCM receive 6 ms frame. The delay is programmed in RCLK bit intervals,
in the range of 1 to 1,024 bits. A value of zero equals one RCLK bit delay. The minimum
RFIFO_WL value must allow sufficient time to elapse for payload to pass through the RFIFO.
The maximum RFIFO_WL must not allow more than 185 bits to be present in the RFIFO at
any given time.
4.8 Transmit Bit Stuffing Thresholds
The STUFF generator in each HDSL transmit channel makes bit stuffing decisions based upon phase
comparisons of the difference between PCM transmit 6 ms frames and HDSL transmit 6 ms frames, with
respect to two programmable Stuffing Thresholds [STF_THRESH and STF_THRESH_C; addr 0xD1–D4].
Results of the phase comparisons determine whether the HDSL channel’s STUFF generator inserts 0 STUFF
bits or 4 STUFF bits in the outgoing HDSL frame. Inserted STUFF bit values are supplied by TSTUFF [addr
0xE4]. The General Purpose Clock (GCLK) is used to quantize phase differences between PCM and HDSL
frame starting locations. GCLK is developed from the MCLK frequency (f_MCLK), PLL Multiplication
(PLL_MUL) and PLL Division (PLL_DIV) scale factors [CMD_1; addr 0xE5]. The STUFF generator makes
bit stuffing decisions using the following criteria:
PCM to HDSL Phase Difference
Inserted STUFF Bits
< STF_THRESH_A
0
≥ STF_THRESH_A
4
< STF_THRESH_C
4
≥ STF_THRESH_C
(1)₄
(1) _{A phase difference measured to be equal to or in excess of STF_THRESH_C is reported as a transmit stuffing error in STUFF_ERR}
[STATUS_3; addr 0x07].
Stuffing threshold values are programmed to set the nominal and maximum tolerable phase difference in
units of GCLK phase. STUFF insertion accounts for ± 4 HDSL bits worth of phase error and STUFF thresholds
are set to equal 16 or 24 HDSL bits worth of phase at the BCLKn frequency (f_HDSL), as shown in the following
equation:
StuffingThreshold
=
n_-----×_-----f_{--M----C----L---K-}
f_HDSL
×
P----L---L----_---M-----U-----L--
PLL_DIV
4-32
Conexant
N8953BDSB