28953-DSH-001-A Datasheet, PDF (115/173 Pages) M/A-COM Technology Solutions, Inc. – HDSL Channel Unit

RS8953B/8953SPB
HDSL Channel Unit
4.0 Registers
4.11 Common Command
0xE8—Command Register 4 (CMD_4)
Must be set to 0x04 before any other MPU access to device, for normal operation. Other values are reserved for
Conexant production test.
0xE9—Command Register 5 (CMD_5)
7
DPLL_NCO
6
5
MASTER_SEL[1:0]
4
3
ZBIT_SEL[1:0]
2
EXT_STUFF
1
0
STUFF_SEL[1:0]
STUFF_SEL[1:0]
Master STUFF source is applicable only if SLV_STUF [TCMD_2; addr 0x07] is enabled. The
slave’s bit stuffing is provided by the master STUFF source.
STUFF_SEL[1:0]
00
01
10
11
STUFF Source
EXT_ STUFF (see below)
HDSL Transmit Channel 1
HDSL Transmit Channel 2
HDSL Transmit Channel 3
EXT_STUFF
NOTE: If SLV_STUF is enabled and is also selected as master, then the master STUFF source
automatically inserts 0 and 4 STUFF bits in alternating frames.
External STUFF—Controls whether 0 or 4 STUFF bits are inserted for slave channels that
select external stuffing. TSTUFF [addr 0xE4] supplies 4 STUFF bit values. The MPU must
write EXT_STUFF at each slave’s transmit frame interrupt.
ZBIT_SEL[1:0]
0 = Insert 0 STUFF bits
1 = Insert 4 STUFF bits
Z-bit Monitor Selection—Applicable only in E1 mode. ZBIT_SEL selects which channel
supplies the last 40 Z-bits to fill the RZBIT_2–RZBIT_6 registers [addr 0x18–0x1C].
ZBIT_SEL[1:0]
00, 01
10
11
Monitor RZBIT[47:8] from
HDSL receive channel 1
HDSL receive channel 2
HDSL receive channel 3
MASTER_SEL[1:0] Master Channel Selection—Selects which HDSL receive channel provides the 6 ms frame
sync signal to the DPLL and PCM formatter. The selected channel’s 6 ms frame is used to
align the PCM receive timebase and to recover the PCM receive clock.
MASTER_SEL[1:0]
00, 01
10
11
Master HDSL Receive Channel
Channel 1
Channel 2
Channel 3
DPLL_NCO
Operates the DPLL as an NCO —The DPLL operates in open loop configuration. Normally,
the DPLL operates in closed loop to recover the PCM receive clock from the master HDSL
receive channel. However, the DPLL may be operated in open loop as a Numerically
Controlled Oscillator (NCO) when the master HDSL reference is unavailable (i.e., during
startup procedure or loss of signal conditions). This bit is only monitored when DPLL is not in
lock.
0 = Closed loop DPLL operation
1 = Open loop DPLL operation
N8953BDSB
Conexant
4-47